Semiconductor device capable of stably generating internal...

Details Semiconductor device capable of stably generating internal... Semiconductor device capable of stably generating internal...

1999-12-08

2001-12-25

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S540000, C323S313000

Reexamination Certificate

active

06333670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device which internally generates a necessary voltage. In particular, the present invention relates to a structure for stably generating an internal voltage under a low power supply voltage level.
2. Description of the Background Art
With development and prevalence of communication and information processing equipments, various semiconductor devices are employed in those equipments. Higher performance is required for such semiconductor devices, while integrity in specification between components is becoming important since the semiconductor device is mounted on a board together with other devices and components. One example of the specification requiring the consistency is a voltage supplied to a plurality of semiconductor devices (components). If all of the devices and components operate with a common voltage, design of a power supply on the board is simplified. Therefore, one semiconductor chip (device) is basically required to operate receiving one kind of supply voltage (except for ground voltage).
However, a voltage having the same voltage level as that of external supply voltage extVdd is not always available as for a voltage supplied to a circuit within the semiconductor device (chip). As the operating speed and integration are advanced, a transistor is considerably decreased in dimension. In the case of MOS transistor (insulated gate field effect transistor), for example, external supply voltage extVdd is too high in view of the reliability of a gate insulating film and the breakdown voltage between the drain and source, and thus cannot directly be used for driving the MOS transistor. Accordingly, external supply voltage extVdd is internally converted to a required voltage level for application to an internal circuit.
FIG. 13
illustrates a structure of a conventional internal voltage down converter VDC. Referring to
FIG. 13
, internal voltage down converter VDC includes a comparator CMP for comparing a reference voltage Vrefs with an internal (power supply) voltage Vdds, and a current drive transistor DR for supplying current from an external power supply node to an internal voltage line according to an output signal of comparator CMP.
Comparator CMP includes p channel MOS transistors Q
1
and Q
2
coupled to the external supply node to supply current, n channel MOS transistors Q
3
and Q
4
receiving current from MOS transistors Q
1
and Q
2
to compare reference voltage Vrefs with internal voltage Vdds, and an n channel MOS transistor Q
5
providing a path for causing an operating current flow through comparator CMP in response to an activation signal VDCON. MOS transistor Q
2
has its gate and drain connected together to the gate of MOS transistors Q
1
, and MOS transistors Q
1
and Q
2
constitute a current mirror circuit.
Current drive transistor DR is constituted of a p channel MOS transistor.
In the structure of internal voltage down converter VDC shown in
FIG. 13
, when activation signal VDCON is at an L (logical low) level, MOS transistor Q
5
is in OFF state, an output signal of comparator CMP is at the level of external supply voltage extVdd, and accordingly current drive transistor DR is in OFF state.
When activation signal VDCON attains an H (logical high) level, MOS transistor Q
5
attains ON state and comparator CMP responsively starts a comparing operation. When internal voltage Vdds is higher than reference voltage Vrefs, an output signal of comparator CMP attains H level so that current drive transistor DR maintains OFF state. When internal voltage Vdds is lower than reference voltage Vrefs, an output signal of comparator CMP lowers so that current drive transistor DR supplies current from the external supply node to the internal voltage line according to the output signal of comparator CMP. As a result, the voltage level of internal voltage Vdds rises. Internal voltage Vdds is thus maintained at the level of reference voltage Vrefs.
Internal voltage Vdds from internal voltage down converter VDC is at the same level as that of reference voltage Vrefs and lower than external supply voltage extVdd, and is supplied to an internal circuit as an operating supply voltage, for example.
Concerning such internal voltage, there are a plurality of kinds in most cases. In a semiconductor memory device, for example, there are two kinds of internal voltages, or the voltage transmitted to a memory array and the voltage for operating peripheral circuitry. Voltage of a required intermediate level is also generated by a voltage down converter as shown in FIG.
13
. Among these internal voltages, a voltage Vrl at a relatively low voltage level is usually used for reducing current consumption.
FIG. 14A
illustrates one example of the usage of voltage Vrl. In
FIG. 14A
, voltage Vrl is utilized for adjusting an amount of current driven by a current source transistor Q
6
of an internal circuit NK. If the level of voltage Vrl is low, the conductance of current source transistor Q
6
is also small so that through current Ic in internal circuit NK can be reduced. In other words, standby current flowing in a standby state can be decreased and accordingly, battery-driven equipments can be operated for a long period of time with one battery.
FIG. 14B
illustrates another usage of internal voltage Vrl. In the structure shown in
FIG. 14B
, transmission gates TG
1
and TG
2
are selectively set into conductive state by switch signal HS to supply one of internal voltages Vh and Vrl to the gate of current drive transistor Q
6
. Internal voltage Vh is higher than internal voltage Vrl.
When switch signal HS is at L level, an output signal of an inverter IV
1
attains H level, and responsively transmission gate TG
1
becomes conductive and internal voltage Vh is supplied to the gate of current drive transistor Q
6
. At this time, operating current (through current) Ic of internal circuit NK increases to allow internal circuit NK to operate at a high speed. On the other hand, when switch signal HS is at H level, an output signal of inverter IV
1
falls to L level, and responsively transmission gate TG
2
becomes conductive and internal voltage Vrl is supplied to the gate of current drive transistor Q
6
and through current Ic is decreased.
According to the structure shown in
FIG. 14B
, the amount of current driven by current source drive transistor Q
6
is adjusted according to an operation mode so as to decrease current consumption in the standby state and to implement a circuit operating at a high speed. Since through current Ic is changed depending on the operation mode switch signal HS, it is unnecessary to place a plurality of current source transistors and set these transistors selectively into ON state according to the operation mode. Consequently, the number of current source transistors can be decreased to reduce the area occupied by the entire circuit.
FIG. 15A
illustrates a further usage of internal voltage Vrl. In the structure shown in
FIG. 15A
, internal voltage Vrl is supplied to the source of an n channel MOS transistor Q
7
. The drain of MOS transistor Q
7
is coupled to receive a supply voltage Vd. Ground voltage GND is supplied to the gate of MOS transistor Q
7
. Internal voltage Vrl is a positive voltage and the gate-source voltage Vgs of the MOS transistor is negative, reducing leakage current (subthreshold current) Ioff. In this case, if back gate bias of MOS transistor Q
7
is lower than internal voltage Vrl applied to the source thereof, substrate-source voltage Vbs increases in a negative direction and the threshold voltage of MOS transistor Q
7
increases owing to the back gate bias effect. Accordingly, subthreshold current ioff can further be decreased.
The voltage application system illustrated in
FIG. 15A
is applied to a memory cell of a DRAM (Dynamic Random Access Memory). The voltage application scheme for decreasing the leakage current is referred to as Boosted Sense Ground (BSG) scheme as discussed by

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