Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-09-14
2001-12-25
Bowers, Charles (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S455000, C438S458000, C438S604000
Reexamination Certificate
active
06333208
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the manufacture of large diameter III-V compound semiconductor wafers used to make semiconductor devices such as FETs (field effect transistors), HBTs (heterojunction bipolar transistors) and MMICs (monolithic microwave integrated circuits).
Among III-V semiconductor compounds, GaAs is most prominent. There has been more extensive device and IC development work and manufacturing infrastructure for GaAs than any other III-V compound semiconductor. Some GaAs devices are in direct competition against silicon devices for application in the commercial market. While much of the discussion below is directed to GaAs, it can also be applied to other III-V compound semiconductors because these other compounds have the same zencblende crystal structure, and have physical and chemical characteristics similar to GaAs.
GaAs, as well as other III-V semiconductor wafers, are much more fragile than silicon wafers. Thus, wafer breakage during device manufacturing is one of the cost disadvantages of GaAs devices and ICs compared to silicon. Another disadvantage of GaAs is that sizes of GaAs wafers available for manufacturing are far smaller than silicon wafers. Currently, the largest size of GaAs wafer available is increasing from 100 mm to 150 mm. However, this increase in wafer size exacerbates the wafer breakage problem.
The density of GaAs is 2.28 times that of silicon. Therefore, a GaAs wafer having a size comparable to a silicon wafer will have more than twice the weight of the silicon wafer. Because such GaAs wafers are more fragile than silicon wafers, and because such GaAs wafers are heavier than silicon wafers, most of the processing machinery originally designed to process silicon wafers may have to be modified if it is used to handle GaAs wafers. Such modifications are generally directed toward slowing the motion of wafers inside the equipment to minimize the likelihood of wafer breakage.
Because GaAs is much denser than silicon, increasing the GaAs thickness to enhance wafer strength is impractical. Further, because of the fracture mechanism of a GaAs single crystal wafer (as well as other III-V semiconductor wafers), making the wafer thicker does not always increase the strength of the wafer proportionally against breakage. This is because III-V semiconductor wafers cleave very easily along {
110
} crystal planes. The cleavage can be initiated from mechanical surface defects, such as scratches from wafer processing or intrinsic material flaws, such as micro voids. A small crack is first formed from these defects or flaws on one of the {
110
} planes which has the smallest cross section (i.e. one of the {
110
} planes perpendicular to the wafer surface). The crack then propagates along the {
110
} plane in response to repeated mechanical impacts and thermal cycling that wafer is subjected to during device processing. The wafer breaks apart when the crack along the {
110
} plane extends across the whole wafer. When that occurs, it occurs most often when the wafer is handled kinetically, e.g. transferring the wafer between cassettes or between a cassette and a machine. If the wafer breaks inside a machine, this not only destroys the wafer, but also may force the shut down of the machine.
After fabrication of devices such as FETs, HBTs and MMICs is done on front side of wafer (the so-called “front side process” in the industry), wafer backside processing follows. The first step of backside processing is wafer thinning by grinding followed by wet chemical etching on the backside of wafer. See, for example, R. E. Williams, “Modern GaAs Processing Methods”, published by Artech House in 1990; and Grupen-Shemansky, et al., “A Novel Wafer Thinning Process for GaAs or Si”, 1994 GaAs MANTECH Conference, pp. 167-170. Although a GaAs wafer is more fragile than silicon, a GaAs wafer needs to be thinned to about 0.1 mm or even 0.03 mm, compared to 0.2 mm to 0.3 mm typically used for silicon wafers. The main reason for such thin GaAs device wafers is that the thermal conductivity of GaAs is only ¼ that of silicon. Another reason is that a thin and precise semi-insulating GaAs substrate thickness is a result of design optimization for strip-line microwave transmission impedance of a MMIC.
A rigid wafer support and front side protection has been developed to aid in the GaAs wafer backside thinning process. See R. E Williams above and Norman, et al., “Substrate Mounting for Wafer Thinning or Substrate Removal, New Technique Factors”, 1992 GaAs Mantech, p. 19-22. To obtain sufficient accuracy in thickness and uniformity, great care is needed during the thinning process.
After wafers are thinned, there are three choices of backside processes before the wafer is scribed and separated into individual devices/ICs:
1. One can do no such additional backside processing if the device/IC will be attached to a metal carrier by an epoxy bond.
2. One can deposit metal on the wafer backside if the device/IC will be attached to a circuit by a solder bond.
3. One can etch small holes extending from the backside of the device/IC to the front side and then deposit metal in the holes to connect device ground (on the front side of the wafer) to the backside metal. This third backside process requires many steps including photo-resist spin and bake, an infrared (“IR”) contact mask to align a mask on one side of the wafer with structures on the other side of the wafer (see R. E. Williams as cited above), and reactive ion etching (“RIE”). To avoid processing these steps on thin and fragile GaAs, it has been proposed to move these processing steps to front side. See Furukawa et al “A Novel Fabrication Process of Surface Via-Holes for GaAs Power FETS”, Tech. Dig. 1998 GaAs IC Symposium, pp251-254, and Ishikawa et al., “A High-Power GaAs FET Having Buried Plated Heat Sink for High Performance MMICs”, IEEE Trans. Electron Devices, Vol. 41, No. 1, 1994, pp. 3-9.) However, this is at a tradeoff cost of requiring a precisely controlled etched hole depth. When using this process, one still cannot avoid the requirement of precise control during backside thinning.
In summary, GaAs wafers are more fragile than silicon. Therefore, the wafers must be handled with greater care. This makes backside processing more complex and difficult.
SUMMARY
A method for reducing the likelihood of a III-V compound semiconductor wafer breaking comprises the step of bonding first and second wafers together. Of importance, the {
110
} cleavage planes in the first wafer perpendicular to the surface of the first wafer are not aligned to any of the {
110
} planes in the second wafer perpendicular to the surface of second wafer. (The symbol {
110
} refers to a family of equivalent crystallographic planes. For example, the (
110
), (
101
), (
011
), (
110
), (
110
), etc. are all members of this family of planes.) The angle of misalignment between such {
110
} planes in two wafers is preferably the maximum allowed by the nature of the zencblende crystal in III-V compounds to maximize the benefit of misalignment in strengthening the bonded wafer to prevent cleavage.
In a preferred embodiment of bonding two wafers with same crystal surface orientation, e.g. a (
100
) orientation, every {
110
} plane in the first wafer perpendicular to the surface of the first wafer is misaligned by about a 45° angle with respect to any corresponding {
110
} plane in the second wafer.
In another embodiment, two wafers with different crystal surface orientations, e.g. an orientation of (
100
) for one wafer and (
111
) for the second wafer, are bonded together. The maximum effective misalignment between two (
011
) planes in the two wafers is 15°. Because the {
110
} planes perpendicular to the wafer surface in the two wafers are misaligned, cleavage along one {
110
} plane of one of the wafers will not propagate to the second wafer's {
110
} plane, and the bonded wafers will e
Bowers Charles
Gurley Lynne
LandOfFree
Robust manufacturing method for making a III-V compound... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Robust manufacturing method for making a III-V compound..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Robust manufacturing method for making a III-V compound... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2598562