Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-07-14
2001-11-13
Nu Ton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
Reexamination Certificate
active
06316977
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge pump. More particularly, the present invention relates to a low charge-injection charge pump for use in low noise, low power, and high speed networking or telecommunications systems.
2. Discussion of the Related Art
Charge pumps are an important element of many electronic circuits such as phase locked loop (PLL) circuits. For example,
FIG. 1
illustrates a typical PLL circuit having a phase-frequency detector
11
and a conventional charge pump and loop filter
21
driving a voltage controlled oscillator (VCO)
31
. When the phase-frequency detector
11
detects that the phase and frequency of a reference clock CKr is greater than the phase and frequency of the feedback clock CK
1
, an UP signal is generated. The UP signal causes the charge pump and loop filter
21
to incrementally increase the output voltage VC
1
thereby increasing the frequency of feedback clock CK
1
. When the phase-frequency detector
11
detects that the phase and frequency of the feedback clock CK
1
is greater than the phase and frequency of the reference clock CKr, a DN signal is generated. The DN signal causes the charge pump and loop filter
21
to incrementally decrease its output voltage VC
1
thereby decreasing the frequency of feedback clock CK
1
. When the reference clock CKr and the feedback clock CK
1
are synchronized, neither the DN signal nor the UP signal is received by the charge pump and loop filter
21
and the voltage VC
1
remains constant.
The structure and operation of a conventional charge pump will now be described. Typically, a charge pump generates an output voltage on a charge summing node by dumping charge onto the node from a current source via a switch, or by sinking charge from the charge summing node to a current sink via a switch. An output voltage VC
1
is generated by the accumulated charge present on the charge summing node.
FIG. 2
shows a conventional charge pump circuit employed by the prior art PLL of FIG.
1
. The conventional charge pump circuit includes a current source
22
, a current sink
26
, an UP switch
23
, a DN switch
25
, and an RC loop filter
28
. The current source
22
is connected between VDD and the UP switch
23
while the current sink
26
is connected between the DN switch
25
and ground. When the UP signal is asserted, the UP switch
23
closes allowing current to flow into the charge summing node, thereby causing the voltage VC
1
to increase. When the DN signal is asserted, the DN switch closes allowing current to flow out of the charge summing node
24
, thereby causing the voltage VC
1
to decrease. An RC loop filter
28
is connected to the output of the charge pump to reduce the speed at which VC
1
varies.
During the time when the UP switch
23
(e.g., a PMOS switch) is turned ON (closed), a channel charge exists in a channel located between the source and drain of the switch
23
. When the switch is turned OFF (opened), the channel collapses causing a portion Qc
1
of the channel charge to flow into the current source
22
and causing a portion Qc
2
of the channel charge to flow into the charge summing node
24
. Likewise, during the time when the DN switch
25
(e.g., an NMOS switch) is turned ON, a channel charge exists in the channel between the source and drain of DN switch
25
. When switch
25
is turned off, the channel collapses causing a portion Qc
4
of the channel charge to flow into the current source
26
and causing a portion Qc
3
of the channel charge to flow into the charge summing node
24
. These charges flowing into the charge summing node
24
introduce undesirable transients on the line between the charge summing node and VC
1
thereby causing the voltage VC
1
to fluctuate. In a case where the output VC
1
of the charge pump drives the control input of a VCO in a PLL, these fluctuations can introduce undesirable jitter in the output clock of the PLL.
A need therefore exists for an improved charge pump that solves the problems described herein by reducing the effect of the voltage fluctuations caused by charge injected electrons and holes disturbing the charge summing node when charge pump switches are turned off.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a charge pump capable of reducing fluctuations in the output voltage. In particular, the present invention provides an apparatus and method of preventing channel charges, present in the drain/source channel of FET switches, from disturbing the voltage on a charge summing node of a charge pump.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a low charge-injection charge pump, comprising a first FET current source, coupled to a charge summing node, for supplying charge to the charge summing node, a first FET switch, switchably coupling the first FET current source to a positive voltage supply, the first FET switch being controlled to supply current to the first FET current source in response to assertion of a first input signal, a second FET current source, coupled to a charge summing node, for removing the charge from the charge summing node, a second FET switch, switchably coupling the second FET current source to a negative voltage supply, the second FET switch being controlled to sink current from the second FET current source in response to assertion of a second input signal, wherein an output voltage of the charge summing node increases in response to the assertion of the first input signal and decreases in response to the assertion of the second input signal, a first biasing circuit that in response to deassertion of the first input signal biases the first FET current source so that the first FET current source does not conduct current, and a second biasing circuit that in response to deassertion of the second input signal biases the second FET current source so that the second FET current source does not conduct current.
In another aspect of the instant invention, there is provided a low charge-injection charge pump, wherein the first biasing circuit includes a third FET switch, switchably coupling a first bias voltage to the first FET current source in response to deassertion of the first input signal and decoupling the first bias voltage from the first FET current source in response to the assertion of the first input signal, and wherein the second biasing circuit includes a fourth FET switch, switchably coupling a second bias voltage to the second FET current source in response to deassertion of the second input signal and decoupling the second bias voltage from the second FET current source in response to the assertion of the second input signal.
In another aspect of the instant invention, there is provided a method for supplying charge to a charge summing node to generate a low noise output voltage by a circuit, the circuit comprising a first FET current source coupled to the charge summing node and a first FET switch for supplying current to the first FET current source, the method comprising the steps of controlling the first FET switch to turn ON so that current is supplied to the first FET current source thereby causing the first FET current source to supply charge to the charge summing node and biasing the first FET current source to cause the first FET current source to turn ON when the first FET switch is turned ON, then controlling the first FET switch to turn OFF so that current is not supplied to the first FET current source thereby preventing the first FET current source from supplying charge to the charge summing node and biasing the first FET current source to cause the first FET current source to turn OFF when the first FET switch is turned OFF.
In another aspect of the instant invention, there is provided a method for supplying charge to a charge summing node, further comprising the steps of coupling a first low impedance path to the first FET switch when the first FET switch is turned OFF so that ch
Morgan & Lewis & Bockius, LLP
Nu Ton My-Trang
PMC-Sierra Inc.
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