Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1999-02-05
2001-10-30
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S107000, C438S118000, C438S126000
Reexamination Certificate
active
06309915
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the art of electronic packaging, and more specifically to assemblies incorporating microelectronic components and methods of making such assemblies.
2. Description of the Related Art
In attempting to use the area on printed wiring boards more efficiently, semiconductor chip manufacturers have switched some of their production from larger more cumbersome interconnection conventions, such as pin grid arrays and perimeter leaded quad flat packs, to smaller conventions such as ball grid arrays (“BGA”) and chip scale packages (“CSP”).
Using BGA technology, semiconductor chips are typically interconnected to an external substrate, such as a printed circuit board, using solder connections, such as with “flip-chip” technology. However when solder alone is used to interconnect the chip contact to the external substrate, the columns of solder are generally designed to be short to maintain the solder's structural integrity. This results in minimal elastic solder connections properties which further results in increased susceptibility to solder cracking due to mechanical stress caused by the differential coefficient of thermal expansion (“CTE”) of the chip relative to the external substrate thereby reducing the reliability of the solder connection. In other words, when the chip heats up during use, both the chip and the external substrate expand; and when the heat is removed, both the chip and the external substrate contract. The problem that arises is that the chip and the external substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them. As the features of the semiconductor chips continue to be reduced in size, the number of chips packed into a given area will be greater and the heat dissipated by each of these chips will have a greater effect on the thermal mismatch problem. This further increases the need for a highly compliant scheme for interconnecting each chip to the external substrate.
Such an interconnection scheme must also be capable of accommodating a large number of interconnection between a single semiconductor chip and an external substrate, such as a printed circuit board. Complex microelectronic devices such as modem semiconductor chips require numerous connections to other electronic components. For example, a complex microprocessor chip may require many hundreds of connections to an external substrate.
Semiconductor chips commonly have been connected to electrical traces on mounting substrates by one of three methods: wire bonding, tape automated bonding and flip-chip bonding. In wire bonding, the semiconductor chip is positioned on a substrate with one surface of the chip abutting the substrate and the face or contact bearing surface of the chip facing upward, away from the substrate. Individual gold or aluminum wires are connected between the contacts on the semiconductor chip and the current conducting pads on the substrate. In tape automated bonding, a flexible dielectric tape with a prefabricated array of leads thereon is positioned over the semiconductor chip and substrate, and the individual leads are bonded to the contacts and pads. In both wire bonding and conventional tape automated bonding, the current conducting pads on the substrate are arranged outside the area covered by the semiconductor chip, so that the wires or leads “fan-out” from the chip to the surrounding current conducting pads. The area covered by the subassembly is considerably larger than the area covered by chip. Because the speed with which a semiconductor chip package can operate is inversely related to its size, this presents a serious drawback. Moreover, the wire bonding and tape automated bonding approaches are generally most workable with semiconductor chips having contacts disposed in rows extending along the periphery of the chip. They generally do not lend themselves to the use of chips having contacts disposed in a so-called area array, i.e., a grid-like pattern covering all or a substantial portion of the chip face surface.
In the flip-chip mounting technique, the contact-bearing surface of the semiconductor chip faces towards the substrate. Each contact on the semiconductor chip is joined by a solder bond to the corresponding current carrying pad on the substrate, as by positioning solder balls on the substrate or contacts on the semiconductor chip, juxtaposing the chip with the substrate in the face-down orientation and momentarily melting or reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. However, flip-chip assemblies suffer from significant problems with thermal stress. The solder bonds between the contacts on the semiconductor chip and the current carrying pads on the substrate are substantially rigid. Changes in the size of the chip and the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the semiconductor chip before attaching it to the substrate and hence difficult to maintain the required outgoing quality level in the finished assembly, particularly where the assembly includes numerous semiconductor chips.
Numerous attempts have been made to solve the foregoing problems. Useful CSP solutions are disclosed in commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390; 5,477,611; 5,518,964; 5,688,716; and 5,659,952, the disclosures of which are incorporated herein by reference.
In preferred embodiments, the structures disclosed in U.S. Pat. Nos. 5,148,265 and 5,148,266, incorporate flexible, sheet-like structures referred to as “interposers” or “chip carriers”. The preferred chip carrier has a plurality of terminals disposed on a flexible, sheet-like top layer. In use, the interposer is disposed on the contact-bearing surface of the chip with the terminals facing upwardly, away from the chip. The terminals are then connected to the contacts on the chip. Most preferably, this connection is made by bonding prefabricated leads on the interposer to contacts on the chip, using a tool engaged with the leads. The completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate. Because the leads and the dielectric layer of the chip carrier are flexible, the terminals on the chip carrier can move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the contacts on the chip or on the bonds between the terminals of the chip carrier and the substrate. Thus, the assembly can compensate for thermal effects. Moreover, the assembly most preferably includes a compliant layer disposed between the terminals on the chip carrier and the face of the semiconductor chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the semiconductor chip. Such a compliant structure permits displacement of the individual terminals independently towards the chip and also facilitates movement of the terminals relative to the chip in directions parallel to the chip surface. The compliant structure further enhances the resistance of the assembly to thermal stresses during use and facilitates engagement between the subassembly and a test fixture during manufacturing. Thus, a test fixture incorporating numerous electrical contacts can be engaged with all of the terminals in the subassembly despite minor variations in the height of the terminals. The substrate can be tested before it is bonded to a substrate so as to provide a tested, known-good part to the substrate assembly operation. This in turn provides very substantial economic and quality advantages.
U.S. Pat. No. 5,455,930 describes a further improvement. Components according to preferred embodiments of the '930 patent use a flexible
Collins D. M.
Lerner David Littenberg Krumholz & Mentlik LLP
Picardat Kevin M.
Tessera Inc.
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