Semiconductor memory device allowing reduction in power...

Details Semiconductor memory device allowing reduction in power... Semiconductor memory device allowing reduction in power...

2000-11-28

2001-10-09

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S194000

Reexamination Certificate

active

06301191

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a synchronous semiconductor memory device which takes in external signals including an address signal and input data in synchronization with an external clock signal, and externally sends storage data. More particularly, the invention relates to a semiconductor memory device having an internal synchronous signal generating circuit such as a PLL (Phase Locked Loop) circuit or a DLL (Delay Locked Loop) circuit which receives an external clock signal and issues a synchronized internal clock signal.
2. Description of the Background Art
In accordance with recent improvement in an operation speed of microprocessors (which will be referred to as “MPUs” hereinafter), it has been proposed to use synchronous DRAMs, which will be referred as “SDRAMs” hereinafter, and operate in synchronization with clock signals in order to achieve fast access of, e.g., dynamic random access memories (which will be referred to as “DRAMs” hereinafter) used as main storage units. Generally, the semiconductor memory device which operates in synchronization with an external clock signal is internally provided with a PLL circuit, a DLL circuit or the like for generating an internal clock signal in synchronization with the external clock signal.
FIG. 41
is a schematic block diagram showing a structure of a synchronous semiconductor memory device
2000
in the prior art.
An external clock signal Ext.CLK applied to a control signal input terminal
2
is sent to an internal synchronous signal generating circuit
50
via a clock buffer circuit
20
. Internal synchronous signal generating circuit
50
issues an internal clock signal int.CLK synchronized with external clock signal Ext.CLK. An internal control signal generating circuit
26
receives internal clock signal int.CLK and issues internal control signals for controlling operations of internal circuitry.
Synchronous semiconductor memory device
2000
further includes an RAS buffer
22
and a CAS buffer
24
, which receive external control signals /RAS and /CAS through external control signal input terminals
4
and
6
and issue an internal row address strobe signal and an internal column address strobe signal controlling operations of the internal circuits, respectively, a memory cell array
10
having memory cells arranged in a matrix form, an address buffer
18
which receives external address signals A
0
-A
1
applied via an address signal input terminal
8
, and is controlled by RAS and CAS buffers
22
and
24
to issue an internal row address signal and an internal column address signal, a row decoder
12
which decodes an internal row address signal sent from address buffer
18
, and selects a corresponding row (word line) in memory cell array
10
, a column decoder
14
which is controlled by the internal control signal sent from internal control signal generating circuit
26
to decode the internal column address signal sent from address buffer
18
, and thereby issues a column select signal for simultaneously selecting a plurality of corresponding columns in memory cell array
10
, a plurality of sense amplifiers which are controlled by the internal control signal sent from internal control signal generating circuit
26
to sense and amplify data of the plurality of memory cells in memory cell array
10
connected to the selected row, an I/O circuit which is controlled by internal control signal generating circuit
26
, and connects a plurality of selected columns in memory cell array
10
to an internal data bus in response to a column select signal sent from column decoder
14
, a selector circuit
28
which is controlled by internal control signal generating circuit
26
to select and issue data among the data of memory cells issued to the internal data bus, and in particular data corresponding to an internal select address applied from address buffer
18
, and an output circuit
30
which is controlled by internal control signal generating circuit
26
to receive an output of selector circuit
28
and issue external output data to data I/O terminal
32
.
In the following description, the sense amplifiers and I/O circuit will be collectively called as a sense amplifier+I/O circuit
16
.
FIG. 42
is a timing chart showing an operation of the conventional synchronous semiconductor memory device
2000
shown in FIG.
41
.
The following description will be given on an operation after a steady state, in which internal clock signal int.CLK synchronized with external clock signal Ext.CLK is issued, is attained after power-on and subsequent start of a synchronizing operation of an internal synchronous signal generating circuit
50
.
In response to a rising edge of external clock signal Ext.CLK at time t
1
, address buffer
18
takes in a row address signal Ax applied through external control signal input terminal
8
. In response to this row address signal Ax, row decoder
12
changes a potential on a word line selected in memory cell array
10
to “H” level. In response to this, and particularly in accordance with storage information in the memory cells connected to the selected word line, the sense amplifiers arranged for the bit line pairs connected to these memory cells amplify the potential differences appearing on the bit line pairs.
After the potential levels on bit line pairs are amplified to a full scale, address buffer
18
takes in a column address Ay through external address signal input terminal
8
at time t
6
, i.e., at a rising edge in a fourth cycle of external clock signal Ext.CLK after time t
1
. In response to this, a plurality of (e.g., four) bit line pairs corresponding to column address signal Ay are connected to I/O line pairs, and the potential levels on bit line pairs are transmitted onto the I/O line pairs.
The storage data read onto the I/O line pairs is sent to selector
28
through the internal data bus. In accordance with the internal control signal sent from internal control signal generating circuit
26
, selector
28
selects data sent from the memory cell, which corresponds to the internal selector address sent from address buffer
18
, and sends the same to output circuit
30
. Output circuit
30
operates in accordance with the internal control signal sent from internal control signal generating circuit
26
, and more specifically sends the latched read data to data I/O terminal
32
at a rising edge of external clock signal Ext.CLK at time t
8
, i.e., at a rising edge in a second cycle of external clock signal Ext.CLK after taking-in of the column address signal into address buffer
18
.
Thus, all the operations, i.e., taking-in of the address signal, reading of data and writing of data in the synchronous semiconductor memory device
2000
are controlled by the internal control signals which are issued from internal control signal generating circuit
26
in accordance with internal clock signal int.CLK issued from internal synchronous signal generating circuit
50
. In particular, the timing of data output is synchronized with external clock signal Ext.CLK, and data issued to data I/O terminal
32
is supplied, as read data, into an external device such as an MPU at a falling edge of external clock signal Ext.CLK.
The description has been given on an example, in which four cycles of the external clock signal are required between taking-in of the row address and subsequent taking-in of the column address, and two cycles of the external clock signal are required between taking-in of the column address and subsequent data output. However, these numbers of cycles depend on a frequency of the external clock signal, an operation speed of the internal circuitry of synchronous semiconductor memory device
2000
and others.
FIG. 43
is a circuit diagram showing a structure of the PLL circuit of the conventional internal synchronous signal generating circuit
50
.
Referring to
FIG. 43
, a power supply node
51
a
is supplied with a power supply potential Vcc, and a ground potentia

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