Semiconductor integrated circuit comprising step-up voltage...

Details Semiconductor integrated circuit comprising step-up voltage... Semiconductor integrated circuit comprising step-up voltage...

2000-04-24

2001-12-11

Wong, Peter S. (Department: 2838)

Electric power conversion systems

Current conversion

With voltage multiplication means

C363S059000, C327S540000, C327S589000

Reexamination Certificate

active

06330173

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a semiconductor integrated circuit comprising a circuit generating a step-up voltage.
2. Description of the Background Art
A DRAM (dynamic random access memory) employs a step-up voltage VPP having a higher level than an external power supply voltage EXTVCC for driving a word line and/or for an output circuit.
As shown in
FIG. 14
, a conventional VPP generation circuit generating such a step-up voltage VPP includes a sensing part
90
sensing the level of the step-up voltage VPP, a ring oscillator
95
and a pumping circuit
96
.
When the step-up voltage VPP falls below a prescribed reference voltage level, the sensing part
90
senses this and generates an enable signal VPPOSCE enabling the ring oscillator
95
.
As shown in
FIG. 15
, the ring oscillator
95
is formed by a NAND circuit
97
and a plurality of serially connected inverters
98
#
1
to
98
#
6
. The NAND circuit
97
receives the enable signal VPPOSCE and an output of the inverter
98
#
6
. When the ring oscillator
95
operates, the inverter
98
#
6
outputs a pulse waveform (pulse signal &phgr;) of a constant cycle.
Referring again to
FIG. 14
, the pumping circuit
96
performs pumping on the basis of the pulse signal &phgr; generated from the ring oscillator
95
. Thus, charges are supplied to a VPP node for supplying the step-up voltage VPP. Consequently, the step-up voltage VPP corresponding to a prescribed reference voltage VREFD is obtained.
The sensing part
90
includes a sensing circuit
91
operating in a standby state and a sensing circuit
92
operating when an act command ACT is issued (in operation, i.e., when an external row address strobe signal/RAS is low).
As shown in
FIG. 16
, the sensing circuit
91
includes a comparator
74
provided between the external power supply voltage EXTVCC and a node N
1
, a constant current source
75
provided between the node N
1
and a ground voltage GND and an inverter
76
.
The comparator
74
is formed by transistors
70
and
71
, a transistor
72
receiving the voltage VPPn obtained by dividing the step-up voltage VPP in its gate electrode and a transistor
73
receiving the reference voltage VREFD in its gate electrode. The inverter
76
inverts a signal on a node N
2
between the transistors
71
and
73
and outputs the enable signal VPPOSCE.
As shown in
FIG. 17
, the sensing circuit
92
is formed by a comparator
74
, a constant current source
79
, a transistor
80
provided between a node N
1
and the constant current source
79
for receiving the act command ACT in its gate electrode and an inverter
76
.
As a current flowing to the comparator controlled by the constant current source is increased, the response speed (the time required for the signal VPPOSCE to go high after the step-up voltage VPP falls below the reference voltage VREFD) of the sensing circuit is increased.
In order to improve the response when receiving the act command, therefore, the constant current source
79
feeding a large current (about 10 &mgr;A) is employed for the sensing circuit
92
. On the other hand, the constant current source
75
feeding a small current (about 2 &mgr;A) is employed for the standby sensing circuit
91
for reducing power consumption.
As shown in
FIG. 18
, a conventional VREFD generation circuit
850
generating the reference voltage VREFD includes a constant current source
84
, a resistive element
85
and a PMOS transistor
86
with the ground voltage GND in its gate electrode.
Assuming that the array voltage VDDA which is employed for writing high-level information in a memory cell, is 2.5 V, for example, the step-up voltage VPP must be set to about (VDDA+2|Vtn|)=4.5 V, where Vtn represents the threshold voltage of a memory cell transistor.
The constant current source
84
, the resistive element
85
and the transistor
86
are connected between the external power supply voltage EXTVCC and the ground voltage GND. A node N
4
between the constant current source
84
and the resistive element
85
outputs the reference voltage VREFD. Assuming that I represents the current of the constant current source
84
, R represents the resistance value of the resistive element
85
and Vtp represents the threshold voltage of the transistor
86
, the reference voltage VREFD is expressed as follows:
VREFD=R×I+|Vtp|  (1)
Assuming that the step-up voltage VPP is 4.5 V, the voltage to be sensed is (½×VPP) and the absolute value |Vtp| is 0.8 V, however, the following equation (2) must be satisfied from the equation (1):
(R×I)=1.45V  (2)
In order to form the VREFD generation circuit
850
according to the equation (2), a resistive element having a high resistance value is necessary. Therefore, the resistive element must be formed by a transistor having a large gate length, disadvantageously leading to a large layout area. When increasing the absolute value |Vtp| of the threshold voltage in order to solve this problem, the reference voltage VREFD may conceivably be varied with the temperature due to high temperature dependency of the absolute value |Vtp|.
Further, the reference voltage VREFD output from the VREFD generation circuit
850
is independent of a voltage related to a memory cell array, as shown in the equation (1). Therefore, when the array voltage is increased (particularly by temperature dependency in a test mode or a general operation mode), for example, the difference (VPP−VDDA) is reduced. Thus, charges written in the memory cell are disadvantageously reduced.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit having a small layout area, which can change a step-up voltage VPP in response to the voltage of a memory cell array area.
The semiconductor integrated circuit according to the present invention comprises a memory cell array area including a plurality of memory cells arranged in rows and columns, a plurality of word lines provided in correspondence to the rows and a plurality of bit lines provided in correspondence to the columns, a voltage generation circuit generating a voltage to be supplied to the memory cell array area and a step-up voltage generation circuit for generating a step-up voltage, and the step-up voltage generation circuit includes a sensing circuit sensing a level of the step-up voltage by comparing a voltage generated in accordance with an output from the voltage generation circuit with a voltage obtained by dividing the step-up voltage and a circuit operating in accordance with an output of the sensing circuit for raising the level of the step-up voltage.
According to the aforementioned semiconductor integrated circuit, therefore, the step-up voltage VPP can be changed in response to change of the voltage supplied to the memory cell array area. Further, voltage reduction can be attained by employing the voltage obtained by dividing the step-up voltage when sensing change of the step-up voltage.
Preferably, the step-up voltage is supplied to a selected word line among the plurality of word lines, the voltage generation circuit generates an array voltage to be written in a selected memory cell among the plurality of memory cells, and the sensing circuit includes a step-up voltage dividing circuit dividing the step-up voltage, an array voltage dividing circuit dividing the array voltage, a reference voltage generation circuit generating a reference voltage on the basis of an output of the array voltage dividing circuit and a compare circuit comparing the reference voltage with an output of the step-up voltage dividing circuit.
According to the aforementioned semiconductor integrated circuit, therefore, the reference voltage is generated on the basis of the voltage obtained by dividing the array voltage VDDA. Thus, the step-up v

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit comprising step-up voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit comprising step-up voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit comprising step-up voltage... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2597905