Full swing power down buffer with multiple power supply...

Details Full swing power down buffer with multiple power supply... Full swing power down buffer with multiple power supply...

2000-03-29

2001-12-04

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S112000

Reexamination Certificate

active

06326832

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit and in particular, to an output buffer which isolates the well of an output pull-up transistor from a power supply utilizing a switching component fabricated from standard CMOS components.
2. Description of the Related Art
FIG. 1
shows a diagram of a conventional CMOS driver circuit
10
conveying signals to bus
12
. Driver circuit
10
includes input node
14
receiving a digital input voltage signal of either a logical high value equal to the power supply voltage (V
cc
) present on power supply rail
16
, or a logical low value equal to ground
18
.
Simple driver circuit
10
also includes PMOS pull-up transistor
20
featuring a gate, source, and drain. The gate is in electrical communication with input node
14
. The source is in electrical communication with power supply rail
16
. PMOS pull up transistor
20
is formed within N-well
22
also in electrical communication with power supply rail
16
.
Driver circuit
10
further includes NMOS pull-down transistor
24
featuring a gate, source, and drain. The gate is in electrical communication with input node
14
. The source is in electrical communication with ground
18
. NMOS pull down transistor
24
is formed within P-type substrate
26
that is also grounded.
The drain of PMOS pull-up transistor
20
and the drain of NMOS pull-down transistor
24
are in electrical communication with each other and with output node
28
. Output node
28
is in electrical communication with bus
12
.
During operation of driver circuit
10
, an input voltage signal is applied to the transistor gates through input node
14
. The input voltage signal is either low (ground) or high (power supply voltage). Where the input voltage is equal to the voltage of power supply rail
16
, the gate-to-source voltage (V
gs
) of PMOS pull-up transistor
20
is zero, and PMOS pull-up transistor
20
is deactivated. At the same time, the V
gs
of NMOS pull-down transistor
24
is positive, and transistor
24
is activated. Thus where the input voltage signal is high, the drains of transistors
20
and
24
respectively are pulled to ground, and output node
28
exhibits low voltage.
Conversely, where the input voltage signal is zero, V
gs
of PMOS pull-up transistor
20
is negative and transistor
20
is activated. At the same time, V
gs
of NMOS pull-down transistor
24
is zero and transistor
24
is deactivated. Thus where the input voltage signal is low, the drains of transistors
20
and
24
respectively are pulled to the power supply voltage, and output node
28
exhibits high voltage. The two states of driver circuit
10
are summarized below in TABLE A:
TABLE A
INPUT NODE
P
in
N
in
OUTPUT NODE
High
Off
On
Low
Low
On
Off
High
Occasionally a need arises for more than one driver circuit to communicate on the same bus. Under these conditions, a driver circuit must be capable of operating in three states, with the driver circuit deactivated in the third state to permit other driver circuit(s) to communicate signals along the bus without interference.
Accordingly,
FIG. 2
shows a conventional three-state driver circuit (also known as a high-impedance, or “high-Z”, driver circuit). High-Z driver circuit
100
can be configured in a third, high impedance state, wherein a voltage on input node
114
is precluded from affecting a voltage on buffer output node
128
.
Specifically, high-Z driver circuit
100
includes an output inverter
129
including PMOS output pull-up transistor
120
and NMOS output pull-down transistor
124
. Output inverter
129
corresponds to the simple driver circuit
10
of FIG.
1
. PMOS output pull-down transistor
120
is formed in N-well
122
. Tri-state driver circuit
100
further includes pre-driver circuit
130
including input inverter
132
and first through fourth enable transistors
142
,
144
,
146
, and
147
respectively.
Input inverter
132
includes PMOS input pull-up transistor
134
. The gate of transistor
134
is in electrical communication with input node
114
, and the source of transistor
134
is in electrical communication with power supply rail
116
.
Input inverter
132
further includes NMOS input pull-down transistor
136
. The gate of transistor
136
is in electrical communication with input node
114
, and the source of transistor
136
is in electrical communication with ground
118
. NMOS input pull-down transistor
136
is formed within P-type substrate
126
which is also grounded.
The drain of PMOS input pull-up transistor
134
and the drain of NMOS input pull-down transistor
136
form first and second conductive paths
138
and
140
, respectively. The voltage appearing on conductive paths
138
and
140
is determined by first through fourth enable transistors
142
,
144
,
146
and
147
, respectively.
The gates of first and second enable transistors
142
and
144
are connected to enable input node
148
. The gates of third and fourth enable transistors
146
and
147
connected to enable inverse input node
150
.
When enable input node
148
is high and enable inverse input node
150
is low, first enable transistor
142
and third enable transistor
146
are activated, and second enable transistor
144
and fourth enable transistor
147
are deactivated. This has the effect of placing the drains of transistors
134
and
136
in electrical communication, such that buffer circuit
130
operates in conjunction with output inverter circuit
129
in essentially the same manner as circuit
10
of FIG.
1
. As described above in conjunction with
FIG. 1
, transistors
120
and
124
of output inverter
129
are then selectively activated/deactivated to convey an output voltage to output node
128
equal to the voltage on input node
114
.
Conversely, when enable input
148
is low and enable inverse input
150
is high, driver circuit
100
is placed into a third configuration. In this third configuration, first and third enable transistors
142
and
146
are deactivated, and second and fourth enable transistors
144
and
147
are activated.
This third configuration has the effect of isolating first and second current paths
138
and
140
from one another. Moreover, because second enable transistor
144
is activated, first electrical path
138
between the drain of PMOS input pull-up transistor
134
and the gate PMOS output pull-up transistor
120
is raised to the power supply voltage on power supply rail
116
. Because fourth enable transistor
147
is activated, second electrical pathway
140
is lowered to ground. When driver
100
is thus placed into the third state, appearance of a voltage signal at input node
114
will not affect the voltage at buffer output node
128
. High-Z driver circuit
100
is thus inactive while second buffer structure
152
communications along bus
112
. Operation of the high-Z buffer circuit of
FIG. 2
is summarized in TABLE B below:
TABLE B
INPUT
ENABLE
TRANS.
TRANS.
TRANS.
TRANS.
TRANS.
TRANS.
OUTPUT
NODE
ENABLE
INVERSE
134
136
142 & 146
144 & 148
PATH 1
PATH 2
120
124
NODE
High
High
Low
Off
On
On
Off
Low
Low
On
Off
High
(GND)
(GND)
Low
High
Low
On
Off
On
Off
High
High
Off
On
Low
(V
cc
)
(V
cc
)
High
Low
High
Off
On
Off
On
High
Low
Off
Off
Z
(V
cc
)
(GND)
Low
Low
High
On
Off
On
Off
High
Low
Off
Off
Z
(V
cc
)
(GND)
While the high-Z driver circuit described above in
FIG. 2
is suitable for some applications, it has a number of serious disadvantages.
One problem with the conventional buffer architecture becomes apparent during power down of the circuit.
Referring back to
FIG. 2
, in a power down situation the voltage appearing on power supply rail
116
may be at or close to ground, while a voltage is conveyed to input node
114
by an active device. Under such power down conditions, pre-driver circuit
130
may communicate a corresponding input voltage to the gate of NMOS output pull-down transistor
124
. Simultaneously, it is possible that second buffer structure
152
could transmit a voltage signal on bus
112
, thereby causi

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