Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-04-08
2001-11-06
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S775000, C438S638000
Reexamination Certificate
active
06313536
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device and, in particular, to a semiconductor device having a multilayered interconnection structure.
As one approach to highly-integrated and high-speed semiconductor devices, a multilayered interconnection (or wiring) structure is adopted in which upper and lower wiring patterns in upper and lower wiring layers are connected via a through hole formed in an interlayer (or intermediate) insulator film between the wiring layers. In a conventional semiconductor device having such a multilayered interconnection structure, the through hole has a width narrower than that of the lower wiring pattern. With this structure, the through hole is prevented from overstepping the lower wiring pattern even in occurrence of a positioning error of the through hole or a variation in process condition. Thus, degradation in reliability and decrease in yield are avoided.
However, there is a standing demand for more and more integrated semiconductor devices. To this end, a line pitch must further be narrowed. Under the circumstances, there is no room to maintain the above-mentioned structure that the lower wiring pattern is wider than the through hole Rather, the through hole and the lower wiring pattern are rendered equal in width to each other because restriction is imposed upon narrowing the through hole. This means that no margin is reserved in positioning the through hole with respect to the lower wiring pattern. In this event, the through hole tends to overstep the lower wiring pattern. If the through hole oversteps the lower wiring pattern, the interlayer insulator film of silicon oxide is undesirably exposed and etched in a portion adjacent to a side surface of the lower wiring pattern during the formation of the through hole. In addition, an underlying silicon oxide film under the lower wiring layer is etched also. As a consequence, leakage of electric current may occur between the upper or the lower wiring pattern and a silicon substrate under the underlying silicon oxide film or another wiring pattern of polysilicon or suicide. In the worst case, short-circuiting is caused to occur. This results in degradation in reliability and decrease in yield.
Taking the above into consideration, it is proposed to form a protection film on the side surfaces of the lower wiring pattern. During formation of the through hole, etching slightly beyond a predetermined position where the through hole is to be formed is stopped by presence of the protection film. For example, such technique is disclosed in Japanese Unexamined Patent Publication (JP-A) No. 226054/1992. With this structure, not only the portion of the interlayer insulator film adjacent to the side surface of the lower wiring pattern but also the underlying silicon oxide film under the lower wiring pattern are completely prevented from being erroneously etched. In the above-mentioned publication, the protection film comprises amorphous silicon. Alternatively, the protection film may comprise a high-melting-point metal, such as W and MO, or silicide thereof. The high-melting-point metal or silicide thereof serves to improve a stress migration resistance and an electromigration resistance in case where the lower wiring pattern comprises an Al alloy. The protection film comprising the high-melting-point metal or its compound is disclosed, for example, in Japanese Unexamined Patent Publication (JP-A) No. 58228/1990.
However, the above-mentioned prior art technique is disadvantageous in the following respects.
At first, when the above-mentioned structure has a width narrower than that of the lower wiring pattern as mentioned above, a connection resistance inevitably becomes high.
This is because, following the improvement of a highly integrated structure of the semiconductor device, the through hole becomes finer and smaller in sectional area.
Secondly, when the protection film is formed on the side surfaces of the lower wiring pattern, leak current may possibly occur if the line pitch is narrow. In the worst case, short-circuiting is caused to occur.
This is because, forming the protection film of a conductive material on the side surfaces of the lower wiring pattern is substantially equivalent to widening the lower wiring pattern in correspondence to the thickness of the protection film. In other words, the line pitch is substantially narrowed.
SUMMARY OF THE INVENTION
It is a general object of this invention to provide a semiconductor device having a multilayered interconnection structure which is capable of preventing a decrease in reliability and yield even if a wiring pattern and a through hole are minimized following the improvement of a highly-integrated structure of the semiconductor device.
It is a specific object of this invention to provide a semiconductor device having a multilayered interconnection structure which is capable of preventing a through hole from overstepping a wiring pattern even if the through hole has a width substantially equal to that of the wiring pattern which is capable of avoiding an increase in connection resistance of the through hole.
According to a first aspect of this invention, there is provided a semiconductor device having a multilayered interconnection structure and comprising a first wiring pattern including a main wiring metal having a forward-tapered cross-section, an interlayer insulator film covering the first wiring pattern, an opening formed in the interlayer insulator film to expose at least a part of side walls of the main wiring metal and an upper surface of the main wiring metal, a conductor layer filled in the opening, and a second wiring pattern formed on the interlayer insulator file to be connected to the conductor layer.
According to a second aspect of this invention, there is provided a semiconductor device having a multilayered interconnection structure and comprising a first wiring pattern including a main wiring metal having a forward-tapered cross-section, an interlayer insulator film covering the first wiring pattern, an opening formed in the interlayer insulator film to expose at least a part of side walls of the main wiring metal and an upper surface of the main wiring metal, and a second wiring pattern formed in the opening and on the interlayer insulator film to be connected to the main wiring metal.
According to a second aspect of this invention, there is provided a semiconductor device comprising a first wiring pattern, an interlayer insulator film covering the first wiring pattern and having a through hole leading to the first wiring pattern, and a second wiring pattern formed on the interlayer insulator film to be connected to the first wiring pattern, wherein the first wiring pattern comprises a main wiring metal and a subsidiary wiring metal. The main wiring metal has a forward-tapered cross-section so that the main wiring metal is narrowed in width from a bottom end towards an upper end in a thickness direction thereof. The subsidiary wiring metal covers side surfaces of the main wiring metal and having outer side surfaces substantially parallel to a depth direction of the through hole. The first wiring pattern has, as a whole, a width substantially equal to that of a bottom end of the main wiring metal.
REFERENCES:
patent: 5462893 (1995-10-01), Matsuoka et al.
patent: 5543360 (1996-08-01), Matsuoka et al.
patent: 5679608 (1997-10-01), Cheung et al.
patent: 5773892 (1998-06-01), Morikawa et al.
patent: 5883434 (1999-03-01), Noguchi
patent: 6016012 (2000-01-01), Chatila et al.
patent: 6130482 (2000-10-01), Iio et al.
patent: 2-58228 (1990-02-01), None
patent: 4-226054 (1992-09-01), None
Zhao, B., “A Novel Sub-Half Micron Al-Cu Via Plug interconnect Using Low Dielectric Constant Material as Inter-Level Dielectric”, IEEE Electron Device Letters, Vol. 18, No. 2, pp. 57-9 Feb. 1997.
Chaudhuri Olik
Foley & Lardner
NEC Corporation
Weiss Howard
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