Sense amplifier/comparator circuit and data comparison method

Details Sense amplifier/comparator circuit and data comparison method Sense amplifier/comparator circuit and data comparison method

1999-11-04

2001-02-20

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S065000, C327S077000

Reexamination Certificate

active

06191620

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to electronic logic circuits used in digital processing systems and, more particularly, to a comparator arrangement and method for comparing data represented by digital input signals and data represented by analog input signals.
BACKGROUND OF THE INVENTION
Digital electronic memory cells are accessed using a complementary pair of bit lines. In a read operation from a digital memory cell, both bit lines are placed in an initial charge state, typically at a supply voltage level. The memory cell selected in the read operation maintains the charge level on one bit line, and allows the charge state to decay on the complementary bit line. The full charge state on one bit line and the lower charge state on the complementary bit line represents binary data, either a “1” or a “0”, which was previously stored in the selected memory cell. However, since the lower charge state develops gradually on the complementary bit line, the signals present on the bit lines in a read operation are analog signals rather than digital signals.
A sense amplifier is used to convert the analog signals read from a memory cell to a complementary pair of digital signals, a true signal and a signal comprising the opposite or complement of the true signal. The sense amplifier is connected to receive inputs comprising the analog signals produced from a memory cell. Operation of the sense amplifier circuit is commonly triggered by a sense enable signal which is provided to the sense amplifier circuit at a time when a minimum voltage differential has developed between the analog signals being read from the selected memory cell. Once enabled, the sense amplifier amplifies the analog signals and produces a complementary pair of digital output signals generally through an output inverter arrangement.
In some microelectronic circuit designs, it is necessary to compare the logical states of two different signals or two different sets of complementary signals. The purpose of this comparison may be to decide what logical function needs to be performed further in the data path or logic path. One particular case in which two different sets of complementary signals must be compared is the case where data read from a memory cell is compared to some reference data. A comparator circuit for performing such a signal comparison is commonly constructed from an exclusive OR (“XOR”) logic circuit. The output of an XOR circuit discharges to ground if both its inputs are at the same logical level. If the inputs to the XOR circuit are at different logical levels, then the circuit output charges to the supply voltage level.
One shortcoming of a conventional comparator circuit is that its input signals need to be true digital signals. That is, the comparator input signals must be very close to the supply voltage level (V
dd
) to indicate one logical state or very close to ground potential to indicate the opposite logical state. Thus, when comparing data read from a memory cell to some reference data, the comparator operation is delayed until the analog signals from the memory cell are converted to digital signals.
The delay in a prior art comparator circuit may be described with reference to FIG.
1
.
FIG. 1
shows a prior art comparator circuit
10
used in conjunction with a sense amplifier
12
. Sense amplifier
12
includes a pre-charge circuit
14
while comparator circuit
10
includes a pre-charge circuit
15
. Prior to a read operation, the sense amplifier pre-charge circuit
14
charges the first and second sense amplifier internal nodes,
16
and
17
respectively, to a supply voltage level. In a read operation, the sense amplifier
12
receives the analog data signals at inputs d
1
and d
1
b. For example, assume that the data being read from the respective memory cell (not shown) is represented by a high-level d
1
signal. When this data is applied to the input lines d
1
and d
1
b, the signal at internal node
16
remains substantially at the supply voltage level while the signal at internal node
17
degrades as signal d
1
b degrades through the respective memory cell. Once a sufficient voltage differential has developed between the signals d
1
and d
1
b, a sense enable signal SE is asserted to the sense amplifier
12
. With the sense enable signal SE asserted, internal node
17
discharges to ground potential through N-type transistor
18
and the sense enable transistor
19
. Internal node
16
remains substantially at the supply voltage level. Output inverter
20
inverts the low-level signal at internal node
17
to produce a high-level digital signal A, while output inverter
21
inverts the signal at internal node
16
to produce a low-level digital signal A_. Thus, the sense amplifier converts the analog signals d
1
and d
1
b to the pair of digital signals, A and its complement A_.
Comparator circuit
10
receives the digital signals A and A_ and compares the data represented by these complementary digital signals to a complementary pair of digital reference signals, B and B_. Assume for purposes of example that the data represented by the digital reference signals matches the data represented by signals A and A_. Thus, signal B comprises a high-level digital signal and signal B_ comprises a low-level digital signal. In the compare operation, pre-charge circuit
15
is first deactivated leaving the first and second internal comparator nodes,
23
and
24
respectively, charged to the supply voltage level. The high-level signal A places N-type transistor
25
in a conductive state while the high-level signal B places N-type transistor
26
in a conductive state. Meanwhile, the low-level digital signals A_ and B_ ensure that N-type transistors
27
and
28
are each placed in a nonconductive state. Thus, the charge at internal comparator node
24
discharges through transistors
25
and
26
to generally ground potential, while the charge on internal comparator node
23
remains substantially at the supply voltage level, reinforced through P-type transistor
29
. The low-level signal at internal node
24
is inverted through the comparator output inverter
30
to produce a high-level digital comparator output signal COMP. The high-level voltage signal at node
23
is inverted through inverter
31
to produce the complement output signal COMPB, which in this case comprises a low-level digital signal.
It will be apparent from the discussion above that the comparator
10
is dependent upon the digital output from the sense amplifier
12
. Comparator operation is delayed until sense amplifier
12
produces the digital output signals A and A_. The time required to produce the desired comparison in the illustrated prior art circuit is equal to the time required for sense amplifier
12
to provide its digital output signals A and A_ plus the time for comparator circuit
10
to perform its evaluation on signals A and A_ and reference signals B and B_.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a comparator circuit and data comparison method for providing a comparator output based upon input signals comprising both digital data signals and analog data signals. Another object of the invention is to provide a comparator circuit for performing the desired data comparison more quickly.
The comparator circuit according to the invention includes a comparator network and a comparator enabling device. The comparator network is adapted to receive input data comprising a complementary pair of reference data signals and a complementary pair of analog data signals. An output of the comparator circuit represents a comparison of the data represented by the reference data signals and the data represented by the analog data signals. The comparator output is generated in response to a comparator enable signal which is applied to the comparator enabling device during the time that the input data is applied to the comparator network. The comparator enable signal is applied at a time when the analog data signals have developed a minimum differential level, commo

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