Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-03-12
2001-11-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030
Reexamination Certificate
active
06324118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and, more particularly, to an input/output circuit for inputting/outputting data in synchronization with a clock as well as to a synchronous semiconductor memory device including the input/output circuit.
2. Description of the Background Art
Conventionally, in a data input/output circuit used in a semiconductor device, for example in a semiconductor memory device, a plurality of data to be output are shifted or offset in phase with respect to an internal clock, so as to enable data transfer from the semiconductor memory device at a rate higher than the clock frequency.
As the speed of operation of semiconductor devices has been increased recently, however, there arises a problem of data collision or erroneous data pickup when a plurality of data are interleaved and picked up by an externally connected circuit.
In a very large synchronous semiconductor memory device having as large a memory capacity as 1 G bit, there is considerably large skew in internal signals, especially in a clock controlling the overall operation of the chip, which skew limits the operational frequency of the chip. Especially when an externally input reference clock is received by a clock buffer and addresses, data and commands are received based on the clock, it is necessary to distribute the received clock to respective address, data and command input terminals. Delay involved in the clock distribution limits performance of the chip. Further, at the time of output, if the output buffer is controlled based on the clock, the output is delayed by the amount of clock skew, which may reduce margin of the output data received externally.
As a second problem, the following is experienced in an operation test during manufacturing or before shipment of the product, as the speed of operation of the semiconductor memory device has been increased.
More specifically, as the storage capacity of the semiconductor memory device increases, the time necessary for testing the device increases and, eventually, the cost for the test and manufacturing cost of the product have been increased.
As a measure to address the increased test time associated with increased storage capacity of the semiconductor memory device, efficiency of testing is improved by testing a plurality of semiconductor memory devices in parallel. The increased storage capacity of the semiconductor memory device mentioned above involves increased number of bits of the address signals to be applied to the semiconductor memory device and multiple bits data input/output interface, and therefore the number of pins for control signals and input/output pins per one semiconductor memory device are increased. Accordingly, the number of semiconductor memory devices which can be tested in parallel at one time is limited.
The number of chips of the semiconductor memory devices which can be measured at one time by a tester is determined by the relation between the number of pins of the tester and the number of pins required by the chip, which relation is generally represented by the following equation.
(Number of pins of the tester)/(number of pins required by the chip)>(number of chips measurable at one time)
Further, if the speed of operation of a tester for testing the semiconductor memory device is to be improved along with the improvement of the speed of operation of the semiconductor device, very expensive testing apparatus is necessary, which results in increased cost of testing.
A third problem is that in a synchronous semiconductor memory device attaining reduced cost and improved function by employing complicated system such as BIST (Built In Self Test) and clock generation by DLL (Delay Locked Loop), it is difficult to monitor state of operation of this circuit externally.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an input/output circuit and a synchronous semiconductor memory device having improved operation frequency margin with respect to data input/output.
Another object of the present invention is to provide a synchronous semiconductor memory device of which cost of testing is reduced by reducing the number of terminals used for testing so that the number of chips which can be measured simultaneously by one tester is increased.
An additional object of the present invention is to provide a synchronous semiconductor memory device of which internal circuitry can be tested and evaluated easily, as external monitoring of the states of internal circuits which cannot be directly monitored from the outside in normal operation is made possible through an input/output circuit.
In summary, the present invention provides a synchronous semiconductor memory device including an input/output terminal, an internal circuit and an input/output circuit.
The input/output terminal input/outputs data. The internal circuit stores data. The input/output circuit exchanges data with the outside through the input/output terminal, and exchanges data with the internal circuit through a data bus. The input/output circuit includes a first data holding circuit holding first data, and a second data holding circuit holding second data.
According to another aspect, the present invention provides a synchronous semiconductor device including a first terminal group, a second terminal group, a first internal circuit, a second internal circuit and a test control circuit.
The first terminal group receives as inputs first data group in the normal operation mode, and receives as inputs first data group and second data group time divisionally in accordance with an external clock in a test mode. The second terminal group receives as inputs the second data group in the normal operation mode. The first internal circuit operates in response to the first data group. The second internal circuit operates in response to the second data group. The test control circuit receives the first data group from the first data terminal group and outputs the data group to the first internal circuit and receives the second data group from the second data terminal group and outputs the data group to the second internal circuit, in the normal operation mode, and the test control circuit receives the first data group and the second data group from the first input terminal group and outputs the data groups to the first internal circuit and the second internal circuit respectively, in the test mode.
According to a still another aspect, the present invention provides a synchronous semiconductor memory device including an internal circuit, a first terminal group and a data transmission circuit. The data transmission circuit is provided between the internal circuit and the first terminal group, activated in the test mode and outputs a data group indicating the state of the internal circuit to the first terminal group.
Therefore, a main advantage of the present invention is that operation margin is enlarged, as the clock for the data exchange with the internal circuit can be set independent from the clock for data exchange with the external circuit.
Another advantage of the present invention is that the number of input/output terminals when operation is confirmed in the step of testing can be reduced, and therefore cost for testing can be reduced.
An additional advantage of the present invention is that when BIST or the like is incorporated, internal state can be monitored by the test apparatus, and therefore the result of confirmation of operation is more reliable, and it becomes easier to find cause of any trouble.
REFERENCES:
patent: 6072743 (2000-06-01), Amano et al.
patent: 6115280 (2000-09-01), Wada
patent: 62-211763 (1987-09-01), None
patent: 8-138377 (1996-05-01), None
patent: 9-120672 (1997-05-01), None
“A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay”, T. Saeki et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1665.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Tran M.
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