Transconductance compensation circuit having a phase...

Details Transconductance compensation circuit having a phase... Transconductance compensation circuit having a phase...

2000-05-19

2001-11-27

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S007000

Reexamination Certificate

active

06323692

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to electrical signal filters and, more particularly, to a temperature and process compensation circuit for an electrical signal filter having an improved phase detector.
BACKGROUND ART
There is an ever present demand for analog data signal filters. Many signal filters, such as transconductance (Gm/C) filters, do not have stable gain-bandwidth products. The Gm/C of a signal filter varies with fluctuations in temperature and process characteristics. Process characteristics are physical and/or chemical properties resulting from the manufacturing process. If the Gm/C of the filter is allowed to fluctuate, the transfer characteristic of the filter will become erratic and may drift outside acceptable operating parameters.
Some techniques for adjusting the Gm/C of filters are known. However, in traditional correction circuits, establishing a proper comparison of the frequencies of a reference signal and a feedback signal is problematic. Some aspects of comparing the phase of two similar signals, such as the techniques used in phase lock loop (PLL) circuits, are sometimes useful in connection with the adjustment of Gm/C filters. PLL circuits, sometimes referred to as phase/frequency detectors (PFD), typically have a phase comparator to compare a reference clock signal with a feedback clock signal. As is known, the phase comparators output up and down pulses to regulate a charge pump.
FIG. 16
illustrates a conventional phase comparator
300
. The phase comparator has a first flip-flop
302
and a second flip-flop
304
. Each of the flip-flops
302
,
304
are rising clock edge triggered D-type flip-flops having their D inputs connected to logic high, or Vcc. Each of the flip-flops will reset upon receiving a logic low at a reset input, or R. Clock inputs of the flip-flops
302
,
304
are respectively connected to the reference clock signal and the feedback clock signal. Up pulses will be generated at a Q output of the flip-flop
302
and down pulses will be generated at a Q output of the flip-flop
304
. The up and down pulses are sent to respective inputs of the charge pump. The Q outputs of the flip-flops are also connected to a NAND gate
306
. When up and down pulses are both received by the NAND gate, the output of the NAND gate, or reset signal RST, will go low thereby resetting the flip-flops
302
,
304
. It is noted that in the following examples, illustrated in
FIGS. 17
a
-
21
e
, the frequency of the reference and feedback signals is approximately 25 MHZ (i.e., a period of about 40 nanoseconds). Accordingly, the time (horizontal) axis of the figures is in nanoseconds and the vertical axis indicates whether the waveform is logical high (i.e., about 3 to 5 volts) or logical low (i.e., about zero volts).
Referring to
FIGS. 17
a
-
17
e
, the foregoing operation of the conventional phase comparator
300
is illustrated when the reference and feedback signals are in phase, or coincident. At the rising edges of reference clock signal (clkref in
FIG. 17
b
) and the feedback clock signal (clkfb in
FIG. 17
a
), the Q outputs of the flip-flops
302
,
304
will each go high thereby generating up and down pulses as illustrated in
FIGS. 17
d
and
17
c
respectively. Since both the up and down pulses are high, the reset signal RST (
FIG. 17
e
) output from the NAND gate
306
will go low and reset the flip-flops
302
,
304
causing the up and down pulses to go low.
FIGS. 18
a
-
18
e
illustrate the operation of the conventional phase comparator
300
when the reference clock signal (clkref in
FIG. 18
b
) leads the feedback clock signal (clkfb in
FIG. 18
a
). At the rising edge of the reference clock signal, the Q output of the flip-flop
302
will go high thereby generating an up pulse as illustrated in
FIG. 18
d
. The up pulse will remain high until the flip-flop
302
is reset. After a period of time determined by how much the feedback clock signal lags the reference clock signal (about 10 nanoseconds in the illustrated example), the rising edge of the feedback clock signal will cause the Q output of the flip-flop
304
to go high thereby generating a down pulse as illustrated in
FIG. 18
c
. Shortly after the down pulse goes high, the reset signal RST (
FIG. 18
e
) output from the NAND gate
306
will go low and reset the flip-flops
302
,
304
causing the up and down pulses to go low. It is noted that in the situation illustrated by
FIGS. 18
a
-l
8
e
, the up pulses of longer duration than the down pulses will cause the output of the charge pump to increase as is well known in the art. The output of the charge pump is usually connected to a circuit element(s) to slow the element(s) to bring the feedback clock signal in phase with the reference feedback signal.
FIGS. 19
a
-
19
e
illustrate the operation of the conventional phase comparator
300
when the feedback clock signal (clkfb in
FIG. 19
a
) leads the reference clock signal (clkref in
FIG. 19
b
). As one skilled in the art will appreciate, this situation is analogous to the situation illustrated in
FIGS. 18
a
-
18
e
. More specifically, at the rising edge of the feedback clock signal, the Q output of the flip-flop
304
will go high thereby generating a down pulse as illustrated in
FIG. 19
c
. The down pulse will remain high until the flip-flop
304
is reset. After a period of time determined by how much the reference clock signal lags the feedback clock signal, the rising edge of the reference clock signal will cause the Q output of the flip-flop
302
to go high thereby generating an up pulse as illustrated in
FIG. 19
d
. Shortly after the up pulse goes high, the reset signal RST (
FIG. 19
e
) output from the NAND gate
306
will go low and reset the flip-flops
302
,
304
causing the up and down pulses to go low. It is noted that in the situation illustrated by
FIGS. 19
a
-
19
e
, the down pulses of longer duration than the up pulses will cause the output of the charge pump to decrease as is well known in the art. The output of the charge pump is usually connected to a circuit element(s) to speed up the element(s) to bring the feedback clock signal in phase with the reference feedback signal.
The operation of the conventional phase comparator
300
is adequate under the three situations illustrated in
FIGS. 17
a
-
17
e
,
18
a
-
18
e
and
19
a
-
19
e
. However, when either the reference or feedback clock signal is missing for one or more cycles, the conventional phase comparator
300
will not function properly for use with certain circuits that are not tolerant to phase slipping. A missing clock cycle can occur at any time, but most often occurs at start-up when a reference clock generator starts producing the reference clock signal but circuit components generating the feedback clock signal do not immediately generate the feedback clock signal, and vice versa.
FIGS. 20
a
-
20
e
illustrate the operation of the conventional phase comparator
300
when the reference clock signal is ahead of (leads) the feedback clock signal (compare rising edge
310
with rising edge
311
), but the reference clock signal is missing for a first cycle. Since the reference clock signal is ahead of the feedback clock signal, the proper response is to generate up pulses of longer duration than down pulses to increase the output of the charge pump and speed the feedback clock signal up to be in phase with the reference clock signal. However, as described in more detail below, the actual response of the conventional phase comparator
300
in this situation is to generate down pulses of very long duration compared to the up pulses. This will decrease the output of the charge pump and start to slow the feedback clock signal. This result may be acceptable in a circuit which can compensate for an adjustment in frequency where a phase slip of a compete cycle is acceptable to bring the feedback and reference signals in phase, such as in many PLL circuits. However, many circuits cannot tolerate such a phase slip. In addition, very long down pulses (i.e, over half a cycle) ma

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