Method of forming low leakage current borderless contact

Details Method of forming low leakage current borderless contact Method of forming low leakage current borderless contact

1999-06-25

2001-10-16

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S400000, C257S344000

Reexamination Certificate

active

06303465

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor manufacturing in general, and more specifically to methods for forming low leakage current borderless contact.
2. Description of the Prior Art
The major objectives of the semiconductor industry have been to continually increase the device and circuit performances of silicon chips, while maintaining or even decreasing the cost of producing these same silicon chips. These objectives have been successfully addressed by the ability of the semiconductor industry to fabricate silicon devices, with sub-micron features. The ability to use sub-micron features, or micro-miniaturization, has allowed performance improvements to be realized by the reduction of resistances and parasitic capacitances, resulting from the use of smaller features. In addition, the use of sub-micron features results in smaller silicon chips with increased circuit densities, thus allowing more silicon chips to be obtained from a starting silicon substrate, thus reducing the cost of an individual silicon chip.
The attainment of micro-miniaturization has been basically a result of advances in specific semiconductor fabrication disciplines, such as photolitography and reactive ion etching. The development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron features in photoresist layers to be routinely achieved. In addition, similar developments in the dry etching discipline have allowed these sub-micron images in photoresist layers to be successfully transferred to underlying materials, which are used for the creation advanced semiconductor devices. However, the use of sub-micron features can improve silicon device performance and decrease silicon chip coast, but will introduce specific semiconductor fabrication problems and will not encounter with larger featured counterparts. For example, specific designs, which are used to connect and overlying metallization structure to an underlying metallization structure, sometimes require that metal filled via holes in insulator layers, and not always be fully landed. That is the result of the metal filled via not being placed entirely on the underlying metallization structure. The inability of fully land a via on an underlying metal structure, places a burden on the process used to create the via hole. For example if the chip design demands a non-fully landed, or has a borderless contact, the dry etching procedure used to create the via has to be able to insure complete removal of insulator materials from the area where the via landed on the underlying metal structure. Therefore, the dry etching procedure necessitates the use of an overetch cycle.
However, overetching can create problems.
FIG. 1A
to
FIG. 1D
are schematic representations of structures at various stages during the formulation of borderless contact using conventional, prior art techniques. A substrate
100
is provided with a source/drain junction
110
formed therein, as shown in
FIG. 1A. A
shallow trench isolation (STI)
120
is formed beside the junction
110
. Then, a silicon nitride layer
140
is deposited on the substrate
100
as a stop layer, as shown in
FIG. 1B. A
planarized interlevel dielectric layer
150
is subsequently formed over the stop layer
140
. The formulation of contact includes two etching steps, i.e.; etching interlevel dielectric layer
150
is the first and etching stop layer
140
is the second.
FIG. 1C
shows the first step and
FIG. 1D
shows the second step. While in the second step, the selectivity between silicon nitride and silicon oxide is about 1.5:1. This will make overetching on top surface of STI
120
near bottom of junction
110
, and leakage current will occur between side wall of STI
20
and substrate
100
when tungsten or copper plug filling the contact
160
, as shown in FIG.
1
D.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming borderless contact that substantially prevents from leakage current caused by overetching of interlevel dielectric.
In one embodiment, a substrate is provided with an active region and a trench formed therein. Then, the trench is etched to stop at a depth. A conformal silicon oxide layer is deposited on the substrate, and a conformal stop layer is subsequently deposited over the silicon oxide layer. As a key step, the stop layer is etched to form spacer against top corner of the trench. Then, a planarized dielectric layer is formed on the substrate. and an opening is etched in the dielectric layer to form borderless contact, wherein the opening overlies both a portion of the trench and a portion of the active region.


REFERENCES:
patent: 6018180 (2000-01-01), Cheek et al.
patent: 6074927 (2000-06-01), Kepler et al.
patent: 6133105 (2000-10-01), Chen et al.

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