Method for joining wafers at a low temperature and low stress

Details Method for joining wafers at a low temperature and low stress Method for joining wafers at a low temperature and low stress

1998-11-30

2001-11-13

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S458000

Reexamination Certificate

active

06316332

ABSTRACT:

FIELD OF THE INVENTION
The invention pertains to the field of joining dissimilar materials together. More particularly, the invention pertains to joining two semiconductor wafers together at a low temperature and low stress when the wafers have different thermal expansion coefficients and lattice constants.
BACKGROUND OF THE INVENTION
Wafer-joining technology is a technology which can integrate various properties from different materials into one compact process-compatible material system. The technology has great potential to innovate the current high technology industries. For example, joining GaAs or InP to silicon can result in the integration of optical and electronic devices and enhance the performance of computers and other electronic systems, because GaAs and InP have direct bandgaps suitable for semiconductor lasers whereas silicon, the most widely used material for electronic devices, has an indirect bandgap unfavorable to optoelectronic devices. In another application, because GaAs has the state-of-art quantum efficiency for solar cells but is more than twice as heavy as silicon, the joining of GaAs films with silicon substrates reduces the solar cell weight to half what it would be with other materials. The availability of high efficiency, light weight GaAs-on-Si solar cells makes more cost effective satellites which are completely powered by solar cells.
In heteroepitaxy, GaAs film is directly grown on silicon by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD). The epitaxial growth takes place above 600° C. in a furnace. The thermal expansion coefficient of GaAs is 6.8×10
6
/° C. which is more than twice that of silicon (2.6×10
6
/° C.). Researchers in the NTT Opto-electronics Laboratories found that when the furnace cools down, high density dislocations of 10
7
/cm
2
are generated. Such high density dislocations in a GaAs crystal degrades any minority carrier devices made with it. ( Appl. Phys. Let. 56, May 28, 1990 pp 2225).
MIT Lincoln lab (Liau et al.) have disclosed a wafer fusion technique in Appl. Phys. Let. 56, 1990, pp 737, successfully infusing GaAs and InP together at a high temperature. In their process, a GaAs wafer and an InP wafer were pressed together with extreme pressure at 750° C. in the presence of phosphine (PH3). Phosphine provides a saturated phosphorous atmosphere to prevent decomposition of the phosphorous from the InP wafer. Covalent bonds are formed between GaAs wafer and InP wafer. These bonds make the wafers stick strongly to each other.
Bellcore (Lo et al.) disclose in U.S. Pat. No. 5,207,864 a direct wafer bonding technique performed at a relatively low temperature and low pressure. GaAs and InP wafers are dipped in diluted HF acid to remove the native oxide on the surfaces. Then, GaAs and InP wafers are put together with a pressure of 200 g/cm
2
in a furnace at 650° C. Hydrogen flows during the process to keep surfaces from oxidizing again. Atoms at the interface between the GaAs and InP wafers migrate to lower the interface free energy and strong covalent bonds form at that temperature.
These techniques are not suitable to transfer a GaAs film to a silicon substrate because GaAs and silicon have a big difference in thermal expansion coefficients. Although the bulk GaAs wafer and silicon wafer can be fused together at temperatures above 550° C., huge stress builds up when the wafers are cooled to room temperature due to the big difference in thermal expansion coefficients. When the GaAs wafer is thinned down to a film level for device fabrication, the built-in stress is totally exerted on that film. The thin film cannot stand such huge stress, whereupon it cracks as reported in the wafer joining of silicon and sapphire disclosed in Appl. Phys. Let. 70, Jun. 2, 1997 pp 2972. Researchers Roberds et al. from Sandia National Laboratories disclose a technique in the proceedings of the Fourth International Symposium on “Semiconductor Wafer Bonding: Science, Technology, And Applications” (
Electrochemical Society Proceedings,
Volume 97-36 pp 592). The researchers lowered the bonding temperature to 300° C.~450° C. while using plasma to activate the surface of the GaAs and silicon wafers so that they could be bonded together. However, the built in stress was still great enough to break the GaAs film into fragments when the GaAs wafer was lapped down to 50 &mgr;m.
At room temperature, cleaned GaAs and silicon wafers can stick to each other by Van Der Waals bonds, but the bonding strength is too weak to allow further processing of the joined wafers. When the bonded GaAs and silicon wafers are heated up to 170 C., they debond. In addition, this bonding cannot withstand wet-etching, since the solution gets into the interface to make the wafers debond at room temperature.
A successful approach transferring GaAs film to silicon substrate, called eutectic-metal-bonding(EMB), is disclosed by Venkatasubramanian et al. from Research Triangle Institute in Appl. Phys. Let. 60(7), Feb. 17, 1992 pp 886. GaAs film is successfully hetero-grown on a Ge substrate by MOCVD at temperatures above 700° C. because GaAs and Ge are lattice matched and also have very similar thermal expansion coefficients. After the growth, a film of gold is evaporated onto the surface of the epitaxial GaAs layer and a clean silicon wafer. Then, the two Au-coated wafers are stacked face to face in intimate physical contact in an alloying furnace, where they are annealed at ~430° C. According to the reference, the bonding of the GaAs layer on Ge substrate to the silicon wafer occurs by the formation of low-temperature eutectics of Au—Si and Au—GaAs. Following the alloying, the Ge substrate is selectively removed by a CF
4
/O
2
plasma-etching process, leaving the GaAs film on the silicon substrate.
This method of bonding requires an alloying furnace and a step of alloying at ~430° C. The eutectics formed during the alloying also result in stress built into the GaAs film. The use of the gold element introduces deep levels in the silicon which is not suitable for further making MOS devices on the silicon. In this disclosure, the growth of the GaAs film was a hetero-growth on a Ge substrate instead of a homo-growth on GaAs, the motivation for which is probably that the interface after EMB cannot stand wet-etching to remove the GaAs substrate. Instead, Ge has to be employed because Ge can be etched by CF
4
/O
2
plasma.
SUMMARY OF THE INVENTION
The method of the present invention is used to join two dissimilar materials together, and particularly to transfer a film to a substrate when the difference in thermal expansion coefficients between the film and the substrate is very big. A hydrophilic surface is created on one material and an atmosphere reactive metal element is deposited on the surface of another material. When the materials are tightly contacted, with the reactive element pressed against the hydrophilic surface, the reactive metal element reacts with the moisture from the hydrophilic surface at room temperature. Strong bonds form during the reaction joining the two materials together. Because the procedure takes place at room temperature, extremely low stress is built in. The film joining is successful even with a big thermal expansion coefficient difference between the materials, such as exist between GaAs and silicon and between silicon and sapphire. The joined materials can sustain typical post-joining device process such as OMCVD growth, wet and dry etching, thin film deposition, and thermal annealing.


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Liau, Z.L. et al, 1990, Wafer fusion: A Novel Technique for Optoelectronic Device Fabrication and Monolithic Integra

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