Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-07-18
2001-11-27
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S254000, C330S256000, C330S257000
Reexamination Certificate
active
06323732
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated amplifier circuits.
BACKGROUND OF THE INVENTION
The gain of conventional integrated amplifier circuits is typically influenced by changes in temperature and process variations that may occur during fabrication. For example, the gain of the bipolar emitter coupled pair (ECP) differential amplifier illustrated by
FIG. 1
is typically a function of the beta (&bgr;) of the bipolar transistors therein. As understood by those skilled in the art, &bgr; may be influenced significantly by changes in temperature and by variations in bipolar fabrication processes. The voltage gain (A
v
) of the ECP differential amplifier of
FIG. 1
is frequently expressed as:
A
v
=&bgr;R
c
I
e
/(&bgr;+1)V
t
(1)
where V
t
is the thermal voltage (V
t
=KT/q). Equation (1) illustrates that the voltage gain is strongly dependent on the value of &bgr; for relatively small &bgr;.
As illustrated by
FIG. 2
, a common technique for limiting fluctuations in the voltage gain of an ECP differential amplifier includes the use of a compensation resistor, R
comp
, in a bipolar current mirror which generates the bias current I
bias
. The inclusion of the compensation resistor provides some degree of beta compensation by increasing the voltage on the base of Q
4
and thereby increasing the collector current in Q
4
. However, to provide adequate compensation, the size of R
comp
frequently has to be relatively large, which may increase the chip area required by the differential amplifier. Compensation resistors also typically have parameters that vary with temperature and such variations can also contribute to gain error. In addition, the bipolar transistors within the current mirror of
FIG. 2
can consume relatively large amounts of power.
Attempts have also been made to substitute MOS devices for the bipolar devices of
FIG. 2
in order to reduce power consumption requirements in current mirrors. For example,
FIG. 3
illustrates a conventional ECP differential amplifier having a MOS-based current mirror therein that generates a bias current (l
bias
) at a level equal to (N)(IREF), where IREF denotes a magnitude of a reference current provided by a fixed current source of conventional design and N designates the mirror gain (e.g., width of NMOS transistor M
6
relative to the width of NMOS transistor M
5
). MOS-based current mirrors can provide additional benefits over bipolar-based current mirrors, including higher output impedance, lower compliance voltage and lower noise. MOS-based current mirrors may also require less decoupling capacitance and typically have improved scaling capability relative to bipolar-based current mirrors. Nonetheless, MOS-based current mirrors typically do not provide significant built-in compensation for &bgr; variations and because of the high gate impedance of MOS transistors compensation resistors typically may not be used successfully.
Thus, notwithstanding the above-described circuits for biasing and compensating differential amplifiers, there continues to be a need for improved biasing circuits that can have low power consumption requirements and can provide excellent compensation for &bgr; variations.
SUMMARY OF THE INVENTION
Preferred differential amplifier embodiments include biasing circuits therein that can automatically account for process and/or temperature induced variations in &bgr; and thereby more uniformly maintain the voltage gain of the differential amplifier at a desired level. According to one preferred embodiment, a differential amplifier is provided that comprises first and second bipolar transistors electrically coupled together as an emitter-coupled pair (ECP) and a biasing circuit that is electrically connected to first and second emitters of the first and second bipolar transistors, respectively. This biasing circuit includes a current mirror that sets a magnitude of an emitter bias current in the first emitter at a value proportional to (&bgr;+1+Z)/(&bgr;+1), where &bgr; is the gain of the first bipolar transistor and 1≦Z≦2. In this manner, the gain of the differential amplifier can be set at a level proportional to (&bgr;
2
+&bgr;(Z+1))/(&bgr;
2
+2&bgr;+1) which is a relatively weak function of &bgr;, even for small &bgr;.
According to another preferred embodiment, a differential amplifier is provided that includes first and second bipolar transistors electrically coupled together as an emitter-coupled pair and first and second current sources that generate a first reference current (IREF
1
) and a second reference current (IREF
2
), respectively. First and second current mirrors are also provided. The first current mirror generates a compensation current having a magnitude proportional to IREF
1
/(&bgr;+1), where &bgr; is the gain of the first bipolar transistor. The second current mirror, which is electrically connected to first and second emitters of the first and second bipolar transistors, sets a magnitude of an emitter bias current in the first emitter at a level proportional to (IREF
2
+(N
1
)(IREF
1
/(&bgr;+1)), where N
1
is a current gain of the first current mirror. To provide a preferred level of &bgr; compensation, the magnitude of (N
1
)(IREF
1
) is preferably set at a level equal to IREF
2
. Thus, Z=1, where Z=(N
1
)(IREF1)/(IREF
2
). These first and second current mirrors also operate to set a magnitude of an emitter bias current in the first emitter at a value proportional to (&bgr;+2)/(&bgr;+1) when Z=1.
According to still another preferred embodiment, a differential amplifier is provided that comprises first and second bipolar transistors electrically coupled together as an emitter-coupled pair and a biasing circuit that is electrically connected to first and second emitters of the first and second bipolar transistors, respectively. The biasing circuit includes first and second current sources that generate a first reference current (IREF
1
) and a second reference current (IREF
2
), respectively. A pair of current mirrors are also provided. A first current mirror generates a compensation current having a magnitude proportional to IREF
1
. A second current mirror is electrically connected to first and second emitters of the first and second bipolar transistors, respectively, and sets a magnitude of an emitter bias current in the first emitter at a level proportional to a sum of IREF
2
and a magnitude of the compensation current. The magnitude of the compensation current is preferably set at a level sufficient to achieve a magnitude of an emitter bias current in the first emitter at a value proportional to (&bgr;+Z+1)/(&bgr;+1) when combined with IREF
2
.
REFERENCES:
patent: 3987368 (1976-10-01), Ahmed
patent: 4064463 (1977-12-01), Leidich
patent: 4929909 (1990-05-01), Gilbert
patent: 4990803 (1991-02-01), Gilbert
patent: 6163215 (2000-12-01), Shibata et al.
patent: 6252458 (2001-06-01), Shibata
Angell Christopher W.
Montalvo Antonio
Ericsson Inc.
Myers Bigel & Sibley & Sajovec
Nguyen Patricia T.
Pascal Robert
LandOfFree
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