Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-09-10
2001-02-06
Shalwala, Bipin (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C348S674000, C348S771000
Reexamination Certificate
active
06184852
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to spatial light modulators, and more particularly to circuits for driving such modulators. The invention is particularly though not exclusively suitable for use with the type of spatial light modulator which has become known as a deformable mirror device or DMD.
For a background description of several types of spatial light modulator reference may be made to HUIGNARD, J. P., “Spatial Light Modulators and their Applications, J. Optics (Paris), 1987, Vol. 18, No. 4, pp 181-186. By way of example another type of spatial light modulator is described in THOMAS, R. N. et. al. “The Mirror-Matrix Tube:A Novel Light Valve for Projection Displays”, IEEE Transactions on Electron Devices, Vol. ED-22, No. 9, September 1975, pp 765-775.
The deformable mirror device is a particular type of spatial light modulator and comprises a micro-mechanical array of electronically addressable mirror elements, the elements corresponding to pixels. Each pixel mirror element is capable of mechanical movement in response to an electrical input. Such movement is in practice more often a deflection rather than a deformation but the term deformable mirror device has now become accepted as the description of this class of devices. They may be digitally addressed in which case they can be referred to as digital mirror devices. The expression DMD covers all of these.
For a description of current DMD technology reference is made to HORNBECK, L. J., “Deformable-Mirror Spatial Light Modulators” Proc. SPIE Critical Reviews Series, Vol. 1150, 6-11 August 1989, San Diego, Calif., U.S.A., pp 86-102. This paper contains many references to earlier work and attention is drawn particularly to references 3, 9, 14 and 23 of that paper. Further details of the construction of the devices is found in BOYSEL, R. M., “A 128×128 frame-addressed deformable mirror spatial light modulator” Optical Engineering, Vol. 30, No. 9, September 1991, pages 1422-1427. Attention is also drawn to reference 1 in that paper which is an earlier publication by Boysel et al. It has been proposed that DMDs should be usable as projection displays, see e.g. HORNBECK, L. J., et al., “Deformable Mirror Projection Display”, SID 80 Digest, pp 228-229 (Abstract of presentation delivered Jul. 20, 1980 at SID Symposium), and U.S. Pat. No. 4,680,579.
The construction and manufacture of DMDs is further described in U.S. Pat. Nos. 4,615,595 and 4,566,935 and European Patent Application EP-A-0 391 529, all of Texas Instruments Incorporated.
The following description assumes a knowledge of the above-noted prior documents, all of which are hereby incorporated by reference.
A DMD may comprise an area array of deflectable mirrors, used to modulate the light in an optical projector. There is one mirror for each picture point or pixel and each mirror is approximately 20 microns square. It is termed digital because each mirror has two positions, an “on” and an “off” position. In the “on” position, incoming light is directed through the projection lens to the display screen, and in the “off” position, light is deflected away from the projection lens, so that no light reaches the screen.
The “on” and “off” positions of each mirror are controlled by two deflection electrodes, which exert an electrostatic attraction on the mirror according to which of the electrodes has been charged with the necessary bias. in addition, there is a common bias applied to all the mirrors, to hold them in their “on” or “off” positions after the potential on the deflection electrodes has leaked away. Therefore the sequence for applying new positional information to each mirror is as follows. Just before the change, the potential on each deflection electrode could be equal, especially if some time has elapsed since the previous change, but the mirrors will remain locked in their previous position because of the common mirror bias. New potentials are now applied to all the deflection electrodes over a relatively short period of approximately 60 to 80 microseconds, but during this time the mirrors stay locked in their previous positions because of the common mirror bias. After all the deflection electrodes have been recharged, the common mirror bias is removed for approximately 10 microseconds and the mirrors are now attracted by the bias present on the deflection electrodes and will change position if this bias is different from the previous setting. The common mirror bias then returns which locks the mirrors in the new position until the next time the common mirror bias is removed.
The magnitude of the light from each pixel is controlled by varying the “on/off” mark space ratio, in other words, the proportion of time in a “frame” period for which each mirror is “on”. If a picture is to be displayed at 50 “frames” per second, each “frame” period will be 20 milliseconds, and the maximum amount of light would be obtained if a mirror was “on” for 20 milliseconds each frame period. To reduce the number of times the mirrors are reset during a frame period to a sensible number, the “on/off” times follow a binary pattern, a frame period being divided into binary fractions of ½,¼, ⅛, {fraction (1/16)}, {fraction (1/32)}, {fraction (1/64)}, etc. The use of such a binary series in a display device is known from United Kingdom Patent Applications Nos. GB-A-2014822A and 2164776A.
If there are 10 binary fractions (10 bits), it would be possible to obtain 1023 levels of brightness from black to maximum brightness, by the suitable selection and addition of the 10 binary fractions, and new information would be injected on 10 occasions during each frame period. 10 bits or 1023 grey scale levels is probably the minimum requirement and even this resolution is a problem since to obtain the first level, it is required that a mirror is switched “on” for the fraction 1/1024 of a frame period of 20 milliseconds, which is approximately 19.5 microseconds. The first problem is that it takes approximately 10 microseconds to switch the mirrors, which is comparable with the “on” time, and the second problem is transferring data into the array during this 19.5 microseconds for the next bit in the sequence.
The input picture data sequence is standardised to suit the raster scan of a cathode ray tube, the 10 bits for the first pixel in the top left hand corner arriving first and so on. The DMD mirror array on the other hand requires that all the lower significant bits in the frame are loaded at a different time to the most significant bits, and thus there is a store to re-arrange the data.
The data output rate from the store is constant, but the data into the array is loaded in 10 variable periods and in one case mentioned earlier, one bit of the frame data must be loaded in 19.5 microseconds or the fraction {fraction (1/1024+L )} of a frame period. The data rate during this time is much greater than that leaving the store and this is accommodated by “first in/first out” (FIFO) memories. Data is clocked in at a constant rate from the store, and is clocked out in bursts to satisfy the requirements of the mirror array. The FIFO's need to store over half a frame of picture data and the number of transistors required in the FIFO integrated circuit is so large that it cannot be integrated with the mirror array and therefore the FIFO's are fabricated separately and added to the mirror substrate later. There is a limit to the number of connections between the FIFO's and the mirror array, and a mirror array operating on the 625 line standard would require 576 lines each with 1024 pixels assuming the pixels are square and the picture has an aspect ratio of 16:9. Therefore there is a requirement for 1024 connections between the FIFO's and the mirror array which is too many in practice. This is reduced to 256 by a demultiplexer and as a result, each of the FIFO's 256 outputs must produce four times 576 bits in 19.5 microseconds, to load the required data during the least significant bit display period. This gives a clock out frequency of
Gillespie John
Millward John David
Digital Projection Limited
Kilpatrick & Stockton LLP
Lewis David L.
Russell, Esq. Dean W.
Shalwala Bipin
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