Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
1997-03-28
2001-10-09
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S462000, C438S700000, C438S113000, C438S114000
Reexamination Certificate
active
06300223
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor structure and its fabrication method, and, more particularly, to a die seal structure around a chip die for preventing the internal circuit of the chip die from the lateral stress induced during the period of cutting wafers, and its fabrication method.
2. Description of the Related Art
In the semiconductor process, a plurality of dies, each of which contains an integrated circuit, are fabricated on a semiconductor wafer at a time. Scribe lines are provided between every two adjacent dies so that the dies can be separated by cutting the semiconductor wafer along these scribe lines.
However, when a wafer is cut into a plurality of dies, lateral stress is induced, thereby affecting the internal circuits via the structure of the IC. Consequently, microcracking may occur and further affect the production yield. One approach for solving such a problem is to form a die seal structure between the scribe line and the peripheral region of the internal circuit. Therefore, stress induced by cutting wafers is generally blocked by the die seal and will not directly impact the internal circuit of a die.
FIG. 1
shows a top view of a chip die. The die seal is directed to the structure between internal circuit
10
and scribe line
50
. The die seal structure comprises buffer area
20
, seal ring
30
and buffer space
40
. Seal ring
30
, which is a stacked structure comprising metal layers and dielectric layers, is usually formed together with the multi-metal interconnection process.
FIG. 2
(PRIOR ART) and
FIG. 3
(PRIOR ART) illustrate two cross-sectional views of the conventional die seal structures, respectively. It is noticed that the die seal structures shown in FIG.
2
and
FIG. 3
are formed together with a triple-metal interconnection process. Now referring to
FIG. 2
, the whole structure is formed on silicon substrate
4
. Field oxide
12
is used as an isolation structure and also can be used to separate a die seal structure (comprising buffer area
20
, seal ring
30
and buffer space
40
) and internal circuit
10
. Seal ring
30
comprises three dielectric layers
14
,
16
and
18
, wherein dielectric layer
16
is formed over dielectric layer
14
, and dielectric layer
18
is formed over dielectric layer
16
. Each of dielectric layers
14
,
16
and
18
is covered with metal layers
15
,
17
and
19
, respectively, which are formed together with the triple-metal process. Finally, passivation layer
22
is formed and covers all the dielectric layers and the metal layers. In summary, seal ring
30
of conventional die seal structure shown in
FIG. 2
is produced by alternately depositing the dielectric layers and the metal layers. It should be noted that these dielectric layers and metal layers are formed during the common semiconductor process and do not require extra steps. In general, seal ring
30
has a width of about 20 &mgr;m, buffer area
20
between internal circuit
10
and seal ring
30
has a width of about 25 &mgr;m, and buffer space
40
between seal ring
30
and the scribe line has a width of about 3~50 &mgr;m.
The die seal structure shown in
FIG. 3
is quite similar to that shown in
FIG. 2
, except in the following aspects. In
FIG. 3
, seal ring
30
includes three metal layers
32
,
34
and
36
, as in
FIG. 2
, and further includes metal plugs
31
,
33
and
35
, located between these metal layers. In this seal ring structure, metal layers
32
,
34
and
36
and metal plugs
31
,
33
,
35
are also formed during the common metalization and plug-in process and do not require extra steps. Therefore, metal plugs
31
,
33
and
35
are usually made of tungsten. Such a seal ring structrure is utilized in the die seal structure to enhance robustness to sawing stress, thereby preventing the internal circuit from damage.
In the development of process techniques, a technique called global planarization is commonly utilized. The most common one is CMP (chemical-mechanical polishing). When CMP is utilized in the fabrication process of semiconductors, the protection ability of the die seal may be reduced. The reason for this will be discussed in the following detailed description. When an inter-metal dielectric layer is planarized by using CMP, the dielectric layer between seal ring
30
and scribe line
50
may not be completely removed in the etching of the contact window, metal via, and passivation, and may accumulate continually on the buffer space. As shown in FIG.
2
and
FIG. 3
, dielectric material
24
on the buffer area
40
may have a depth of about 12000 Å in the prior art. The residual dielectric material on buffer area
40
may be a path of stress when a wafer is sawed. Thereby, the reliability of dies may be reduced.
On the other hand, the stress can reach internal circuit
10
via dielectric material
24
and substrate
4
. In the prior art, the die seal structure can not provide complete protection to internal circiuts.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a new structure of a die seal capable of preventing the stress from being transmitted via the dielectric material and the substrate and damaging the internal circuit in the die.
Another object of the present invention is to provide a method of fabricating the new structure of the die seal.
In order to achieve these objectives, the present invention provides a die seal having trenches. The structure of the die seal formed on a silicon substrate can be used to prevent lateral stress, which may damage the internal circuit in a die. The die seal comprises a buffer space, a die seal and a buffer area. The buffer area is adjacent to the internal circuit. The buffer space is adjacent to a scribe line. The seal ring stacked by at least one metal layer and at least one dielectric layer is located between the buffer area and the buffer space. There is no dielectric layer stacked on the buffer space having a trench on a substrate. The trench is used for enhancing the stress-protection ability of the die seal, and is formed by etching. The trench is formed by wet-etching SiO
2
residues on the buffer space using buffered HF, or wet-etching Si
3
N
4
residues on the buffer space using phosphoric acid at 180° C. In addition, the portion of the substrate may be removed by wet etching using HNO
3
and HF. On the other hand, dry etching may also be used to remove the residual dielectric material and substrate. For example, a mixture gas of CHF
3
, SF
6
and He, or the fluorocarbon-containing gas can be used in the reactive ion etching (RIE) process to etch SiO
2
or Si
3
N
4
. The mixture gas of CF
4
and Ar, or fluorocarbon-containing gas, or the mixture gas of Cl
2
and BCl
3
may be used in the reactive ion etching process to etch the silicon substrate.
REFERENCES:
patent: 5024970 (1991-06-01), Mori
patent: 5414297 (1995-05-01), Morita et al.
patent: 5530280 (1996-06-01), White
patent: 5559362 (1996-09-01), Narita
patent: 5665655 (1997-09-01), White
patent: 5698892 (1997-12-01), Koizumi et al.
patent: 5772906 (1998-06-01), Abraham
patent: 5831330 (1998-11-01), Chang
patent: 5891808 (1999-04-01), Chang et al.
Chang Gene Jiing-Chiang
Chen Chun-Cho
Bowers Charles
Chen Jack
Ladas & Parry
Winbond Electronics Corp.
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