Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1999-10-14
2001-12-11
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S028000, C712S034000
Reexamination Certificate
active
06330658
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer and data processing arrangements. More particularly, the invention relates generally to task allocation between multiple processors and accelerating performance of stack-based processors in such arrangements.
BACKGROUND OF THE INVENTION
Platform-independent programming languages, such as the “Java” programming language from Sun Microsystems, Inc., offer significant advantages over traditional, platform-specific languages. A platform-independent programming language typically utilizes platform-independent program code (machine-readable instructions) suitable for execution on multiple hardware platforms without regard for the particular instruction set for the hardware platforms. A hardware platform typically includes a computer system having one or more processors (e.g., microprocessors or microcontrollers) which execute a particular set of instructions having a specific format, sometimes referred to as a native instruction set. This is in contrast to platform-specific languages, which utilize platform-specific compilers to generate program code that is native to one particular hardware platform. While the same source code may in some instances be compiled by different platform-specific compilers into suitable program code for multiple platforms, the resulting program code is not platform-independent.
Most platform-independent program code is in an intermediate code format, since further processing is required to execute it on a specific hardware platform. For Java, for example, the intermediate codes are referred to as bytecodes. Typically, a compiler is used to generate a series of intermediate codes from a source file. The intermediate codes are then executed by a software interpreter which converts them into native instructions for the computer system on the fly Consequently, the intermediate codes are executable on any computer system having a suitable interpreter.
Many platform-independent program codes are relatively compact, which makes them readily suited for downloading over a network or modem. Moreover, since the program code is platform-independent, the downloading computer system (or server) can download the same program code irrespective of the particular hardware platform of the executing computer system (or client). Consequently, platform-independent program codes such as Java are expected to enjoy immense popularity for the distribution of software programs over the Internet. Typically, platform-independent software programs downloaded from the Internet are in the form of applets which execute within a web browser. It should be understood, however, that platform-independent program code has many other uses, including in stand-alone applications, operating systems, and real-time embedded systems, among others.
One problem with platform-independent program code, however, is that the program code must be interpreted during run time, which significantly reduces execution speed compared to program code native to a particular hardware platform. Some Java interpreters, for example, may require up to 50 processor clock cycles to process each bytecode, compared to typically one clock cycle for most native instructions.
As an alternative to run time interpretation, software-based just-in-time (JIT) compilers have been developed to optimize interpretation of platform-independent program code, typically by emulating the functionality of the platform-independent code using native code. While execution speed is increased over simple runtime interpretation, the platform-independent program code is still slower than native code, and additional memory space is required to store the compiler code.
At the other extreme, dedicated processors (e.g., for Java, the picoJAVA, microJAVA and UltraJAVA processors from Sun Microelectronics) have been proposed to utilize platform-independent instructions as their native instruction set. While these processors may have the capability of running platform-independent program code as fast as other native program codes for other hardware platforms, the processors suffer from the same problems as any other processor when executing non-native program code.
Moreover, because many of the architectures for dedicated processors are stack-based (see, e.g., the Java Virtual Machine Specification), significant performance limitations exist in these processors since frequent memory accesses are required to access a stack. Much of the computer industry has moved away from stack-based architectures in part due to the memory and performance bottlenecks presented by the use of a stack.
It is estimated that in the future as much as 50% or more of the program code run on any particular hardware platform may be platform-independent. However, a large portion of program code will still be platform specific. Consequently, a substantial need exists for a manner of accelerating the execution of platform-independent program code on a hardware platform without adversely impacting the execution speed of native program code thereon.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, there is provided a circuit arrangement, which includes a slave processor and a master processor. The slave processor includes a control unit configured to process instructions received by the slave processor, an internal control register arrangement configured to provide at least one of several operational states for the slave processor, a program counter register in the internal control register arrangement configured to point to an address of a next instruction to be processed by the control unit, and a control register access port coupled to the internal control register arrangement to provide external access thereto. The master processor is coupled to the slave processor, and is configured to selectively start execution of the slave processor with a predetermined operational state by writing data into the internal control register arrangement through the control register access port to modify the program counter register.
In accordance with another aspect of the invention, a computer system is provided, which includes a slave processor and a master processor. The slave processor includes a control unit configured to process instructions received by the slave processor, an internal control register arrangement configured to provide at least one of several operational states for the slave processor, a program counter register in the internal control register arrangement configured to point to an address of a next instruction to be processed by the control unit, and a control register access port coupled to the internal control register arrangement to provide external access thereto. The master processor is coupled to the slave processor, and is configured to selectively start execution of the slave processor with a predetermined operational state by writing data into the internal control register arrangement through the control register access port to modify the program counter register.
In accordance with a further aspect of the invention, a method is provided for controlling with a master processor the operation of a slave processor coupled to the master processor. The method includes setting an operational state of the slave processor with the master processor by programming an internal control register arrangement in the slave processor, the internal control register arrangement configured to provide the operational state for the slave processor, and the internal control register arrangement including a program counter register; and starting execution of the slave processor with the master processor.
The above summary of the present invention is not intended to describe each illustrated embodiment, or every implementation, of the present invention. This is the purpose of the figures and the detailed description which follow.
REFERENCES:
patent: 4876643 (1989-10-01), McNeill et al.
patent: 4888680 (1989-12-01), Sander et al.
patent: 5036453 (1991-07-01), Renner et al.
patent: 5073854 (1991-12-01),
Evoy David Ross
Levy Paul S.
Koninklijke Philips Electronics , N.V.
Maung Zarni
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