Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2000-01-19
2001-02-20
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S403000, C438S406000, C438S933000, C148SDIG001
Reexamination Certificate
active
06191006
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a direct bonding method for bonding a III-V group compound semiconductor layer on a silicon substrate.
Recently, attention to a direct bonding method for of a III-V group compound semiconductor layer such as an InP layer on a silicon substrate has been on the increase in place of the heteroepitaxial growth. The heteroepitaxial growth has disadvantages in large lattice mismatch causing at high density crystal defects such as threading dislocations and in a large difference in thermal expansion coefficients which may provide a large thermal stress. The direct bonding method has been developed to prevent the above disadvantages of the heteroepitaxial growth, but the following serious problems still remain.
The bonding of the III-V group compound semiconductor layer requires a heat treatment at a relatively high temperature to cause atomic re-arrangements on a bonding interface for secure bonding. This high temperature heat treatment and subsequent cooling stage may raise other serious problems. The III-V group compound semiconductor layer has a large difference in thermal expansion from the silicon substrate. The heat treatment for bonding the III-V group compound semiconductor layer on the silicon substrate and subsequent cooling stage thereof may introduce a large thermal stress due to the difference in the thermal expansion coefficient between the III-V group compound semiconductor and the silicon substrate. The thermal stress may introduce various crystal defects such as dislocations into mainly the III-V group compound semiconductor layer acting as a device layer. The III-V group compound semiconductor layer having many crystal defects such as dislocations, particularly threading dislocations is not usable. If a low temperature heat treatment is carried out for bonding the III-V group compound semiconductor layer on the silicon substrate, it is difficult to obtain a necessary large bonding intensity.
It has been required to provide a novel method of bonding III-V group compound semiconductor layer on the silicon layer free from introduction of any crystal defects such as dislocations but is able to obtain a strong bonding intensity.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a novel method for bonding a III-V group compound semiconductor device on a silicon substrate.
It is another object of the present invention to provide a novel method for bonding a III-V group compound semiconductor device on a silicon substrate being able to prevent crystal imperfections of III-V group compound semiconductor layers.
It is yet another object of the present invention to provide a novel method for bonding a III-V group compound semiconductor device on a silicon substrate being able to secure a strong bonding intensity.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
The present invention provides a novel method for bonding a III-V group compound semiconductor layer to a silicon layer. The III-V group compound semiconductor layer has a different thermal expansion coefficient from a thermal expansion coefficient of the silicon layer and has a different rigidity coefficient from a rigidity coefficient of the silicon layer. The novel method includes at least the following steps.
An intermediate layer sandwiched between the silicon layer and the III-V group compound semiconductor layer is prepared to subsequently subject the intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C., provided that the intermediate layer comprises a thermal stress relaxation layer having a thermal expansion coefficient equal or near to the thermal expansion coefficient of the III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in the III-V group compound semiconductor layer due to a thermal stress generated in the heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer.
It is a still further preferable to form at least a semiconductor contact layer between the III-V group compound semiconductor layer and the thermal stress relaxation layer, provided that the semiconductor contact layer has a rigidity coefficient being sufficiently small for facilitating atomic re-arrangements in the contact layer by the heat treatment. The semiconductor contact layer may include at least any one of In and Sb.
It is yet a further preferable to form at least an insulation contact layer between the III-V group compound semiconductor layer and the thermal stress relaxation layer to permit a low temperature bonding with a static voltage application.
It is also preferable that the thermal stress relaxation layer is formed on the silicon layer and the III-V group compound semiconductor layer is formed on a supporting substrate made of the same compound semiconductors as the III-V group compound semiconductor layer for subsequent contact of the thermal stress relaxation layer with the III-V group compound semiconductor layer.
It is also preferable that the III-V group compound semiconductor layer is formed on a supporting substrate made of the same compound semiconductors as the III-V group compound semiconductor layer and then the thermal stress relaxation layer is formed on the III-V group compound semiconductor layer for subsequent contact of the thermal stress relaxation layer with the silicon layer.
The present invention also provides a method for bonding a III-V group compound semiconductor layer to a silicon layer wherein the III-V group compound semiconductor layer has a different thermal expansion coefficient from a thermal expansion coefficient of the silicon layer and has a different rigidity coefficient from a rigidity coefficient of the silicon layer. The method may include the following steps.
An intermediate layer sandwiched between the silicon layer and the III-V group compound semiconductor layer is prepared to subsequently subject the intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C., provided that the intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through the strained layer into the III-V group compound semiconductor layer wherein the threading dislocation is caused by a thermal stress generated in the heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer.
The present invention provides a method for bonding a III-V group compound semiconductor layer to a silicon layer wherein the III-V group compound semiconductor layer has a different thermal expansion coefficient from a thermal expansion coefficient of the silicon layer and has a different rigidity coefficient from a rigidity coefficient of the silicon layer. The method comprises the following steps. An intermediate layer sandwiched between the silicon layer and the III-V group compound semiconductor layer is formed to subject the intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C. The intermediate layer comprises an amorphous semiconductor layer capable of preventing a threading dislocation to extend through the strained layer into the III-V group compound semiconductor layer wherein the threading dislocation is caused by a thermal stress generated in the heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer. The amorphous semiconductor layer comprises an amorphous semiconductor being kept in amorphous state even after the heat treatment
Dang Trung
NEC Corporation
Young & Thompson
LandOfFree
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