Sign extension unit

Details Sign extension unit Sign extension unit

1998-11-25

2001-10-30

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S513000

Reexamination Certificate

active

06311199

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sign extension unit for extending a sign bit, i.e., the most significant bit of input data to the higher side of the input data.
2. Description of Related Art
FIG. 1
shows a sign extension circuit
301
according to a related art. The sign extension circuit
301
receives input data of byte length (8 bits), half-word length (16 bits), word length (32 bits), or double-word length (64 bits) and extends a sign bit thereof to form signed 64-bit output data. The circuit
301
has selectors MM
8
to MM
63
to receive input data consisting of bits IN
0
to IN
63
at the maximum. The selectors MM
8
to MM
15
select the bit IN
7
or the bits IN(8+n) (n=0 to 7) and provide the selected bits as output bits OUT
8
to OUT
15
. The selectors MM
16
to MM
31
select the bit IN
7
, the bit IN
15
, or the bits IN(16+n) (n=0 to 15) and provide the selected bits as output bits OUT
16
to OUT
31
. The selectors MM
32
to MM
63
select the bit IN
7
, the bit IN
15
, the bit IN
31
, or the bits (32+n) (n=0 to 31) and provide the selected bits as output bits OUT
32
to OUT
63
. The selection made by the selectors MM
8
to MM
63
is based on the length of input data.
Upon receiving input data of byte length consisting of bits IN
0
to IN
7
, the selectors MM
8
to MM
63
select the bit IN
7
serving as a sign bit of the input data for output bits OUT
8
to OUT
63
, and the bits IN
0
to IN
7
are provided as they are as output bits OUT
0
to OUT
7
. Namely, the sign bit of the input data is extended for the output bits OUT
8
to OUT
63
, and the output bits OUT
0
to OUT
63
form sign-extended 64-bit output data. Upon receiving input data of half-word length consisting of bits IN
0
to IN
15
, the selectors MM
16
to MM
63
select the bit IN
15
serving as a sign bit of the input data for output bits OUT
16
to OUT
63
, the bits IN
0
to IN
7
are provided as they are as output bits OUT
0
to OUT
7
, and the selectors MM
8
to MM
15
select the bits IN
8
to IN
15
as output bits OUT
8
to OUT
15
. Namely, the sign bit of the input data is extended for the output bits OUT
16
to OUT
63
, and the output bits OUT
0
to OUT
63
form sign-extended 64-bit output data. Upon receiving input data of word length consisting of bits IN
0
to IN
31
, the selectors MM
32
to MM
63
select the bit IN
31
serving as a sign bit of the input data for output bits OUT
32
to OUT
63
, the bits IN
0
to IN
7
are provided as they are as output bits OUT
0
to OUT
7
, and the selectors MM
8
to MM
31
select the bits IN
8
to IN
31
as output bits OUT
8
to OUT
31
. Namely, the sign bit of the input data is extended for the output bits OUT
32
to OUT
63
, and the output bits OUT
0
to OUT
63
form sign-extended 64-bit output data. Upon receiving input data of double-word length consisting of bits IN
0
to IN
63
, the bits IN
0
to IN
7
are provided as they are as output bits OUT
0
to OUT
7
, and the selectors MM
8
to MM
63
select the bits IN
8
to IN
63
as output bits OUT
8
to OUT
63
. Namely, the input data is provided as it is as 64-bit output data.
This related art supplies an input bit IN
7
to the 56 selectors MM
8
to MM
63
. Namely, the input bit IN
7
must drive the gates of the 56 selectors, and long wiring must be laid to transmit the input bit IN
7
to the 56 selectors. In this way, the related art applies large load on the input bit IN
7
, to increase signal delay and decrease operation speed.
To solve this problem, there is an idea of inserting buffers in signal paths for transmitting the input bit IN
7
. The buffers, however, cause gate delay and increase the size of the circuit
301
.
In addition, input bits IN
15
and IN
31
must drive large load, and therefore, these bits involve the same problem as the bit IN
7
, although the load on the bits IN
15
and IN
31
is relatively small compared with that on the bit IN
7
.
In this way, the related art applies large load on some bits of input data, to increase signal delay and decrease operation speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a sign extension unit capable of reducing load on paths for transmitting a sign bit. Another object of the present invention is to provide a sign extension unit capable of operating at high speed.
In order to accomplish the objects, the present invention provides a sign extension unit having first and second sign extenders. Input data consisting of input bits to the sign extension unit is divided into blocks of equal number of bits. The first sign extender receives highest bits from the blocks, selects a sign bit of the input data or the received bits according to the bit length of the input data, and provides the selected bits. The second sign extender receives the input bits from the blocks except a lowest one of the blocks, selects the highest bits of the blocks or the input bits according to the bit length of the input data, and provides the selected bits.
The first sign extender may have selectors for receiving the highest bits from the blocks, selecting the received bits or the sign bit of the input data according to data length information related to the input data, and providing the selected bits.


REFERENCES:
patent: 5497341 (1996-03-01), Cohen
patent: 5523961 (1996-06-01), Naini
patent: 6065034 (2000-05-01), Mahurin

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