Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-07-29
2001-02-20
Chang, Kent (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S060000
Reexamination Certificate
active
06191763
ABSTRACT:
The present invention relates to a process for controlling a memory-effect display panel, especially those of large size. Its purpose is to increase the image renewal rate.
DISCUSSION OF THE BACKGROUND
Recent developments in large-size plasma display panels or those for high-definition television have led to a larger resolution and to an ever faster image renewal rate.
Display panels comprise a large number of cells arranged in matrix form in lines and columns. Each cell consists of the gaseous space lying at the intersection of two electrodes belonging to two orthogonal networks of electrodes and is subjected to control signals consisting of the difference of the voltages applied to the two electrodes between which it lies.
The principle of operation of memory-effect panels is generally as follows. A substantially square-wave AC hold signal is applied to all the lines. Its effect is to maintain each cell in the state which was assigned to it previously by an addressing signal. It generates a hold discharge with regard to the cells in the written state.
Addressing is generally carried out by line-by-line scanning. All the cells of a selected line are controlled simultaneously by a more or less complex semi-selective operation so as to be “erased” and this operation is followed by a selective operation during which cells of the line may be “written”. The semi-selective operation followed by the selective operation is accomplished with a time offset from one line to the next.
To obtain 2
a
half-tones, the screen must be scanned a times over the duration T of a complete image. If n is the number of lines of the screen and t the duration for which a line is addressed, the following condition holds:
n.t.a≦T
For example, in a high-definition television type panel operating at 50 Hz with 8 half-tone levels and 1000 lines:
T
=
20
ms
t
≈
20
8
×
1000
≈
25
μs
This duration is close to the physical limits of the duration required to produce a discharge.
If the number of lines and/or the number of half-tones must increase further, a saving in the addressing time becomes paramount in order to satisfy this increase in the image renewal rate.
In a plasma display panel, of AC type, the discharge current is limited by a capacitor in series with each cell so as to avoid destroying the display panel if the power supply is not limited in terms of current. This capacitor is generally produced by covering the electrode network with a dielectric layer of enamel for example.
The erasing of a cell consists in eliminating the charges stored on the dielectric at the cells of the relevant line.
To achieve erasure, a voltage is generally applied to the electrode forming the corresponding line and this causes a discharge whose intensity is chosen in such a way that the charges stored facing one another recombine so as to cancel one another out. The erasing of a cell creates a discharge current whose intensity is substantially equal to half that of the hold current since roughly half of the customary hold charges are transferred.
At the present, the semi-selective erase operation is performed in various ways.
The hold signals are generally a succession of voltage square-waves, between two extreme porches, high and low, possibly with a middle porch. The semi-selective erase address signal has the shape of a voltage pulse, of amplitude suitable to create an erase discharge, which is superimposed on the square-waves of the hold signal. This semi-selective erase addressing signal will actually increase the duration of a hold cycle as compared with that required to effect just the holding.
FIGS. 1
a
,
1
b
,
1
c
show timing diagrams of the hold signal and of the semi-selective erase addressing signal in various cases used at present. The selective write addressing signal is no. represented.
In
FIG. 1
a
, the hold signal Vref (represented as a solid line) comprises two extreme porches, one corresponding to the low potential V
1
(negative) and the other to the high potential V
2
(positive), these porches being established on either side of a middle potential or reference potential V
0
which is often the potential of earth. This hold signal Vref generates discharges with regard to the cells in the written state just after a reversal of polarity, that is to say after an edge leading to an extreme porch. The semi-selective erase addressing signal is a voltage pulse represented as a dashed line, superimposed on the hold signal. The erase pulse is generated during a low porch. The duration of the hold cycle is then equal to:
tca=tb1a+tma+tb2a+tha
with:
tb1a the duration of the low porch before the erase pulse,
tma the duration of the erase pulse,
tb2a the duration of the low porch after the erase pulse,
tha the duration of the high porch.
In
FIG. 1
b
, the hold signal Vref comprises a middle porch of duration tmb lying between two low porches of duration tb1b, tb2b.
The semi-selective erase addressing signal is a pulse superimposed on the hold signal Vref, and generated during this middle porch. Its amplitude Vpb is less than that Vpa represented in
FIG. 1
a.
The duration tcb of the hold cycle is then equal to:
tcb=tb1b+tmb+tb2b+thb
In
FIG. 1
c
, the hold signal Vref comprises a middle porch of duration tcm between a low porch of duration tbc and a high porch of duration thc. The semi-selective erase addressing signal is a pulse of amplitude Vpc generated from this middle porch. The amplitude Vpc is less than that of
FIG. 1
a.
The duration tcc of the hold cycle is then equal to:
tcc=tbc+tmc+thc
The drawback of this type of operation is that the duration of the hold cycle is longer than that which is normally sufficient to effect holding. In the cases represented in
FIGS. 1
a
,
1
b
,
1
c
this duration is increased by the duration tma, tmb, tmc respectively.
The configuration in which the erase pulse is generated from a middle porch has a drawback related to the presence of the middle porch during the hold cycle. Charges may disappear during this middle porch, this disappearance causing a partial loss of the memory of the panel.
Moreover, the generation of the middle porch requires a specific circuit.
The configuration in which the erase pulse is generated from the low porch has a drawback. The amplitude of the pulse to be generated is still large and this pulse can only be generated by a relatively expensive specific circuit.
SUMMARY OF THE INVENTION
The present invention therefore proposes to incorporate the time for the semi-selective erase addressing into the hold cycle without thereby increasing its duration.
To do this, the present invention is a process for controlling a display panel comprising cells defined by the Intersection of two networks of crossed electrodes, these cells possessing two states, one written, the other erased. It consists in applying a substantially square-wave hold signal on either side of a middle potential to all the cells, with the aim of producing a hold discharge with regard to the cells in the written state at the termination of the edges leading to an extreme porch and in applying an addressing signal, superimposed on the hold signal, in succession to the electrodes of a network. The addressing signal comprises a semi-selective erase signal which generates in respect of the cells in the written state an erase discharge.
The erase discharge occurs at the termination of an edge leading to an extreme porch of the hold signal. This erase discharge disables the hold discharge which should have been generated by the hold signal alone.
REFERENCES:
patent: 4650434 (1987-03-01), Deschamps et al.
patent: 4684849 (1987-08-01), Otsuka et al.
patent: 5030888 (1991-07-01), Salavin et al.
patent: 5066890 (1991-11-01), Salavin et al.
patent: 5075597 (1991-12-01), Salavin et al.
patent: 5086257 (1992-02-01), Gay et al.
patent: 5237315 (1993-08-01), Gay et al.
patent: 5247288 (1993-09-01), Warren et al.
patent: 5867135 (1999-02-01), Salavin et al.
pa
Dunand André
Salavin Serge
"Thomson-CSF"
Chang Kent
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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