Pulse or digital communications – Synchronizers
Reexamination Certificate
1998-05-21
2001-12-11
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
C382S304000
Reexamination Certificate
active
06330295
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processing system and a data processing method adopted in the data processing system, and particularly to a data processing system and a data processing method adopted in the data processing system which are capable of keeping up with a case in which the piece count of pixel data to be processed increases by delaying the operating timing of input and output units employed in the data processing system.
As a related art data processing system, there is known a processor called an SVP (Serial Video Processor) described in Section 3.1 on Page 17 of the IEEE 1990 Custom Integrated Circuits Conference. Composed of 1,024 processors integrated in a single chip, the SVP is a processor for carrying out real time digital processing on a video signal. The SVP has an SIMD (Single Instruction stream/Multiple Data stream) structure which allows pixel data on a horizontal scanning line to be processed concurrently. SIMD is the name of one of data processing methods adopted by a computer whereby data of different kinds is processed concurrently as if the data pertained to one job.
FIG. 1
is a block diagram showing a typical configuration of an SIMD control parallel processor. As shown in the figure, the SIMD control parallel processor includes a program control apparatus
17
, an input SAM (Serial Access Memory) unit
11
, a data memory unit
12
, a processing circuit unit
13
and an output SAM unit
14
.
The input SAM unit
11
, the data memory unit
12
, the processing circuit unit
13
and the output SAM unit
14
constitute a group of parallel processor elements
15
arranged in a linear array. The processor elements
15
are controlled in a state being interlocked with each other in accordance with a program of the program control apparatus
17
, that is, subjected to the SIMD control. The program control apparatus
17
includes a program memory for storing the program in advance and a sequence control circuit for carrying on the program. The program control apparatus
17
generates a variety of control signals in accordance with the program in order to control a variety of circuits.
It should be noted that the input SAM unit
11
, the data memory unit
12
, and the output SAM unit
14
are each implemented as a memory, detailed explanation of which is omitted. In an apparatus shown in
FIG. 1
, row address decoders for these memories are included in the program control apparatus
17
.
One processor element
15
is represented by a hatched block in
FIG. 1. A
plurality of processor elements
15
are arranged in parallel, that is, in the horizontal direction of the figure. That is to say, the processor element
15
indicated by the hatch block includes components of one processor.
Next, the operation of the linear array parallel processor for carrying out video processing shown in
FIG. 1
will be described.
Input data, strictly speaking, video data of one pixel, is supplied to the input SAM unit
11
in accordance with a control signal output by the program control apparatus
17
. The processor elements
15
from the leftmost one to the rightmost one shown in the figure sequentially process the data. That is to say, pieces of input data are supplied sequentially to input SAM cells of the input SAM unit
11
from the leftmost one to the rightmost one shown in the figure.
Since the number of the processor elements
15
is at least equal to the pixel count H in one horizontal scanning period of a video signal, pixel data of one horizontal scanning period of a video signal can be accommodated in the input SAM unit
11
. The operation to supply input data is repeated for each horizontal scanning period.
Each time data of one horizontal scanning period of a video signal is accumulated in the input SAM unit
11
as described above, the program control apparatus
17
carries out processing by executing SIMD control on the input SAM unit
11
, the data memory unit
12
, the processing circuit unit
13
and the output SAM unit
14
in accordance with the program as described below. In addition, the SIMD control causes the following operations to be executed in all the processor elements
15
concurrently in the same way.
The input data of one horizontal scanning period of a video signal accumulated in the input SAM unit
11
is, if necessary, transferred from the input SAM unit
11
to the data memory unit
12
during the next horizontal scanning fly-back line period to be used in the subsequent processing.
In a transfer of data from the input SAM unit
11
to the data memory unit
12
, the program control apparatus
17
makes an access to data of a predetermined bit count in the input SAM unit
11
selected by an input SAM read signal, and then outputs a memory access signal to write the data into a predetermined memory cell of the data memory unit
12
.
Next, the program control apparatus
17
supplies data stored in the data memory unit
12
of each processor element
15
to the processing circuit unit
13
of the processor element
15
in accordance with the program and lets the processing circuit unit
13
carry out arithmetic and logic processing on the data supplied thereto. Results of processing are then written at a predetermined address of the data memory unit
12
.
FIG. 2
is a block diagram showing a typical configuration of the processing circuit unit
13
. Pieces of data from the data memory unit
12
are supplied to a register
84
by way of a selector
80
, a register
85
by way of a selector
81
and a register
86
by way of a selector
82
. The selector
80
selects the value
1
set in advance, the piece of data output by the data memory unit
12
or data stored in the register
84
and outputs the selected one to the register
84
. The selector
80
selects one of the three inputs in accordance with a signal generated by the program control apparatus
17
. A register
87
is used for storing data representing a carry-over generated by a full adder
91
.
A logical product circuit
88
computes a logical product of the data stored in the register
84
and data stored in the register
85
. An exclusive logical sum circuit
89
computes an exclusive logical sum of data output by the logical product circuit
88
and data supplied by the program control apparatus
17
and supplies the exclusive logical sum to the full adder
91
. The full adder
91
also receives data stored in the register
86
and data stored in a register
87
. The full adder
91
computes the sum of these three inputs, outputting the sum and its carry-over to a selector
92
. The carry-over is also supplied to the register
87
by way of the selector
83
.
A selector
90
selects either the data output by the register
85
or data output by the register
86
and outputs the selected one to the selector
92
. The selector
92
selects one of three inputs thereof, that is, the data output by the selector
90
, the sum output by the full adder
91
or the carry-over also output by the full adder
91
, and outputs the selected one to the data memory unit
12
. Signals generated by the program control apparatus
17
control how the selectors
90
and
92
select one of their inputs.
Assume that, for example, a signal generated by the program control apparatus
17
controls the selector
80
to let the selector
80
select the value
1
to be stored in the register
84
. In this case, since the logic value
1
is stored in the register
84
, data stored in the register
85
from the data memory unit
12
passes through the logical product circuit
88
as it is, entering the full adder
91
by way of the exclusive sum circuit
89
. The full adder
91
computes the sum of the data supplied from the register
85
by way of the exclusive logical circuit
89
, data stored in the register
86
from the data memory unit
12
and data representing a carry-over generated in previous processing and stored in the register
87
. The sum and a newly generated carry-over are output to the selector
92
. The carry-over is supplied to the register
87
through t
Frommer William S.
Frommer & Lawrence & Haug LLP
Shallenburger Joe H.
Sony Corporation
Vo Don N.
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