Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer handshaking
Reexamination Certificate
1997-06-25
2001-10-16
Harrell, Robert B. (Department: 2152)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer handshaking
C709S224000, C370S468000, C370S504000, C370S516000, C710S261000, C710S269000
Reexamination Certificate
active
06304911
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to providing an interrupt signal to a host system processor unit to indicate that an information packet being received from a communications network requires processing.
2. Description of the Related Art
A great deal of information is transferred over communications networks. Typically, host computing systems, such as personal computers, operate as nodes on a communications network. Each node is capable of receiving information from the network and transmitting information onto the network.
Information is transferred over a communications network in information packets. The organization of information in an information packet, as well as the procedures for forming and combining information packets, are dictated by a network operating system protocol. There are many different protocols in existence. In fact, information frames that correspond to different protocols can coexist on the same communications network.
In order for a node to receive and transmit information packets, it is equipped with a network peripheral. The network peripheral is responsible for transferring information packets between the communications network and the host system.
A processor unit in the host system assists in the transmission of an information packet by constructing the information packet and passing it to the network peripheral. The processor unit assists in the reception of an information packet by retrieving the information packet from the network peripheral and processing it in accordance with a network operating system protocol.
The processor unit performs many of its transmission and reception functions in response to instructions from an interrupt service routine for the network peripheral. When a received information packet requires processing, an interrupt may be issued to the host system by the network peripheral. The interrupt has traditionally been issued after either all of the bytes in an information packet or a fixed number of bytes in an information packet have been received by the network peripheral.
In response to a packet reception interrupt, the processor unit enters the interrupt service routine and executes the necessary instructions for assisting in the packet reception process. Upon responding to the interrupt, the processor unit ceases the operations that it is presently performing and saves the entire status of the host system.
The time period from the network peripheral asserting an interrupt to the processor unit beginning to execute the interrupt service routine is referred to as interrupt latency. Interrupt latency can be a considerable amount of time, approximately 30 &mgr;s-45 &mgr;s in a personal computer. Accordingly, it is beneficial for the processor unit to only receive one interrupt for the reception of an incoming information packet.
It is also beneficial to reduce the utilization of the processor unit in executing the interrupt service routine. If the processor unit receives an interrupt too early in a packet's reception, then the processor unit will process the received portion of the packet and sit idly while the rest of the packet is received by the network peripheral. Decreasing the time that the processor unit has to wait idly in an interrupt service routine allows the processor unit more time to perform other useful tasks, such as executing instructions in application programs.
Asserting an interrupt after an information packet has been completely received by a network peripheral ensures that only a single packet reception interrupt is issued for a received information packet. As a result, only a single interrupt latency must be incurred in the processing of the incoming packet. Additionally, the entire information packet is ready to be processed when the host processor unit begins executing the interrupt service routine. This provides for a reduction in the utilization of the processor unit, since there is little, if any, idle time.
However, waiting until after an incoming information packet has been completely received to assert a packet reception interrupt causes the processing of the information packet to be delayed. Such delay includes the interrupt latency time and/or the time required for the processor unit to execute the interrupt service routine. It is desirable to avoid such delay.
The overall performance of a host system as a node is dependent on how rapidly information packets can be processed once they are detected by the network peripheral. A processor unit's prompt processing of incoming information packets enables a host system to quickly assemble and transmit any information packets that are to be sent in response to received information packets. Further, prompt processing of incoming information packets decreases the amount of memory that is required to be used for storing received information packets that are waiting to be processed.
In order to avoid delay in the processing of incoming information packets, reception indicators in network peripherals have been developed to overlap the reception of an incoming information packet with the interrupt latency. These reception indicators do not wait until after the information packet has been fully received to assert an interrupt. These reception indicators issue an interrupt at a predetermined time before an incoming information packet has been completely received by the network peripheral. In such reception indicators, the predetermined time is approximately equal to the host system's interrupt latency.
As a result, the processor unit is able to begin executing the interrupt service routine for the network peripheral at approximately the same time that the information packet has been fully received by the network peripheral. Unfortunately, the processor unit may still have to execute a significant portion of the interrupt service routine subsequent to the information packet's reception having been completed. Such reception indicators are described in U.S. Pat. No. 5,412,782 (“'782 Patent”) and U.S. Pat. No. 5,307,459 (“'459 Patent”).
The reception indicator disclosed in the '782 Patent provides for an early receive interrupt to be generated by a network peripheral after a predetermined number of bytes of an incoming information packet have been received. The predetermined number of bytes is programmed into an early receive threshold register in the network peripheral by a host system's user. In response to the early receive interrupt, a host processor unit begins executing an interrupt service routine for the network peripheral.
The interrupt service routine instructs the host processor unit to determine if the network peripheral is still receiving any portion of the same incoming information packet. If the information packet has not been fully received, the interrupt service routine instructs the host processor unit to determine the expected total number of bytes in the information packet and program a new value into the early receive threshold register. The new value is equal to the expected size of the incoming information packet minus the number of information packet bytes that the network peripheral can receive during the host system's interrupt latency. After reprogramming the early receive threshold register, the host processor unit processes the received portion of the information packet and then exits the interrupt service routine.
Once the network peripheral receives the number of information packet bytes that has been newly programmed into the early receive threshold register, the early receive interrupt is generated again for the same information packet. Once again, an interrupt latency delay is incurred by the host system before the host processor unit begins executing the interrupt service routine. Ideally, the entire packet has been received by the network peripheral at the time the processor unit begins executing the interrupt service routine for the second time. This allows the processor unit to complete its processing of the information pac
Brcich Joseph A.
Roberts David G.
Williams Robert
Advanced Micro Devices , Inc.
Harrell Robert B.
Willett Steve
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