Oscillator circuit with current limiting devices

Oscillators – Solid state active element oscillator – Transistors

Reexamination Certificate

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Details

C331S109000, C331S158000, C331S182000, C331S183000, C331S074000, C331S175000

Reexamination Certificate

active

06329884

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an oscillator circuit.
2. Description of Related Art
Heretofore, an oscillator circuit for realizing lower power consumption has been provided with a configuration as shown in FIG.
1
. This circuit is described specifically by referring to this figure. A CMOS inverter
101
is connected with a higher-potential power supply
103
and with a lower-potential power supply
104
via current-limiting devices
102
that are used to realize lower power consumption. One electrode of a load capacitor
105
is connected with the input side of the CMOS inverter
101
, while the other electrode is connected with the lower-potential power supply
104
. One electrode of a load capacitor
106
is connected with the output side of the CMOS inverter
101
, whereas the other electrode is connected with the lower-potential power supply
104
. Also shown are a quartz oscillator
107
and a feedback resistor
108
.
In the above-described configuration, however, the load capacitors
105
and
106
directly connected with the power supplies cause the circuit to have the problem that the power-supply voltages vary greatly in synchronism with the oscillation. Therefore, any circuit using a power supply in common with this oscillator circuit has the disadvantage of becoming unstable in operation. Conversely, where the power-supply voltages are varied by some action independent of the oscillation, there is also the disadvantage that the variations adversely affect the oscillator circuit.
SUMMARY OF THE INVENTION
In the present invention, the first load capacitor is connected between the input side of a CMOS inverter and one power-supply potential, the second load capacitor is connected between the input side of the CMOS inverter and the other power-supply potential, the third load capacitor is connected between the output side of the CMOS inverter and the one power-supply potential, and the fourth load capacitor is connected between the output side of the CMOS inverter and the other power-supply potential. Thus, variations in the power-supply voltages in synchronism with oscillation can be reduced with the realization of lower electric current consumption.
Since the first and third load capacitors and one power-supply side of the CMOS inverter are coupled to the one power-supply voltage via the first current-limiting device, and the second and fourth load capacitors and the other power-supply side of the CMOS inverter are coupled to the other power-supply voltage via the second current-limiting device, variations in the power-supply voltages in synchronism with oscillation can be reduced further with the realization of lower current consumption.
The first and second current-limiting devices may be resistors.
The first and second current-limiting devices may be transistors.
The first and second current-limiting devices may be constant current circuits.
Each of the first and second current-limiting devices is made of a plurality of switching devices connected in parallel. These switching devices are controlled by a control circuit according to the output from the CMOS inverter. This therefore enables the current-limiting devices to be adjusted, so that optimum adjustment becomes possible. Moreover, for example, by controlling the switching devices so that a large amount of current flows via these switching devices at the start of oscillation and so that a desired amount of current flows after the oscillation has been stabilized, the time between the start of the oscillation and the stabilization of the oscillation can be shortened to enhance the responsiveness.


REFERENCES:
patent: 5030926 (1991-07-01), Walden

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