Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-10-01
2000-05-16
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438427, 438435, 438437, 438692, 148DIG50, H01L 2176
Patent
active
060636890
ABSTRACT:
A method for forming a shallow-trench isolation starts with forming a polysilicon layer, which has less stress, as the mask layer for patterning the trench on a provided substrate. An oxide layer is then formed to cover the polysilicon layer and fill the trench. The oxide layer is then removed by first performing a chemical mechanical polishing process to remove a portion of the oxide layer, wherein the remains of the oxide layer still covers the polysilicon layer and fills the trench. After that, an etching back process is performed to remove the oxide layer from the top of the polysilicon layer to form the oxide plug, which is used as an isolation.
REFERENCES:
patent: 5721172 (1998-02-01), Jang et al.
patent: 5811345 (1998-09-01), Yu et al.
patent: 5817567 (1998-10-01), Jang et al.
patent: 5854133 (1998-12-01), Hachiya et al.
patent: 5874345 (1999-02-01), Coronel et al.
patent: 5930645 (1999-07-01), Lyons et al.
Chen Coming
Lur Water
Dang Trung
Huang Jiawei
United Microelectronics Corp.
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