Signal processors

Details Signal processors Signal processors

1997-11-26

2001-02-13

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

Reexamination Certificate

active

06188344

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a 1-bit signal processor comprising nth order Delta-Sigma Modulators where n is at least one. Preferred embodiments of the invention relate to processing audio signals but the invention is not limited to audio signal processors.
2. Description of the Prior Art
Background to the present invention will now be described by way of example with reference to
FIGS. 1
,
2
and
3
of the accompanying drawings of which
FIG. 1
is a block diagram of a known Delta-Sigma Modulator,
FIG. 2
is a block diagram of a previously proposed Delta-Sigma Modulator configured as an nth order filter section and
FIG. 3
shows a noise shaping characteristic.
It is known to convert an analogue signal to a digital form by sampling the analogue signal at at least the Nyquist rate and encoding the amplitudes of the samples by an m bit number. Thus if m=8, the sample is said to quantized to an accuracy of 8 bits. In general m can be any number of bits equal to or greater than 1.
For the purpose of quantizing to only 1 bit, it is known to provide an analogue to digital converter (ADC) known either as a “Sigma-Delta ADC” or as a “Delta-Sigma ADC”. Herein the term “Delta-Sigma” is used. Such an ADC is described in for example “A Simple Approach to Digital Signal Processing” by Craig Marven and Gillian Ewers ISBN 0-904.047-00-8 published 1993 by Texas Instruments.
Referring to
FIG. 1
in an example of such an ADC, the difference (Delta) between an analogue input signal and the integral (Sigma) of the 1-bit output signal is fed to a 1-bit quantizer
3
. The output signal comprises bits of logical value 0 and 1 but representing actual values of −1 and +1 respectively. The integrator
3
accumulates the 1-bit outputs so that value stored in it tends to follow the value of the analog signal. The quantizer
3
increases (+1) or reduces (−1) the accumulated value by 1-bit as each bit is produced. The ADC requires a very high sampling rate to allow the production of an output bit stream the accumulated value of which follows the analogue signal.
The term “1-bit” signal as used in the following description and in the claims means a signal quantized to an accuracy of 1 digital bit such as is produced by a Delta-Sigma ADC.
A Delta-Sigma Modulator (DSM) configured as nth order filter section for directly processing a 1-bit signal was proposed by N. M. Casey and James A. S. Angus in a paper presented at the 95th AES Convention Oct. 7-10, 1993 New York, USA entitled “One Bit Digital Processing of Audio Signals” (Signal Processing: Audio Research Group, The Electronics Department, The University of York, Heslington, York YO1 5DD England).
FIG. 2
shows a 3rd order (n=3) version of such a DSM filter section.
Referring to
FIG. 2
, the DSM has an input
4
for a 1-bit signal and an output
5
at which a processed a 1-bit signal is produced. The bits of the 1-bit signal are clocked through the DSM by known clocking arrangements which are not shown. The output 1-bit signal is produced by a 1-bit quantizer Q which is for example a comparator having a threshold level of zero. The DSM has three stages each comprising a first 1-bit multiplier a
1
, a
2
, a
3
connected to the input
4
, a second 1-bit multiplier c
1
, c
2
, c
3
connected to the output
5
, an adder
6
1
,
6
2
,
6
3
and an integrator
7
1
,
7
2
,
7
3
.
The 1-bit multipliers multiply the received 1-bit signal by p bit coefficients A
1
, A
2
, A
3
, C
1
C
2
, C
3
producing p bit multiplicands which are added by the adders
6
1
,
6
2
,
6
3
and the sums passed to the integrators
7
. In the intermediate stages the adders
6
2
,
6
3
also sum the output of the integrator of the preceding stage. A final stage comprises another 1-bit multiplier A
4
connected to the input which multiplies the input signal by a p bit coefficient A
4
and an adder
6
4
which adds the multiplicand to the output of the integrator
7
3
of the preceding stage. The sum is passed to the quantizer
2
.
Within the DSM, two's complement arithmetic is used to represent the positive and negative p bit numbers. The input to the quantizer Q may be positive, quantized at the output as +1 (logical 1) or negative quantized at the output as −1 (logical 0).
As observed by Casey and Angus “a one bit processor . . . will produce a one bit output that contains an audio signal that is obscured by noise to an unacceptable level and it is imperative the quantization noise is suitably shaped”. The noise which obscures the audio signal is the quantization noise produced by the quantizer Q.
The quantizer Q may be modelled as an adder which has a first input receiving an audio signal and a second input receiving a random bit stream (the quantization noise) substantially uncorrelated with the audio signal. Modelled on that basis, the audio signal received at the input
4
is fed forward by multipliers a
1
, a
2
, a
3
, a
4
to the output
5
and fed back by multipliers c
1
, c
2
, c
3
from the output
5
. Thus coefficients A
1
to A
4
define zeros of the Z-transform transfer function of the audio signal and coefficients C
1
-C
3
define poles of the transfer function of the audio signal.
The noise signal, however is fed-back from the quantizer by the multipliers C
1
-C
3
so that coefficients C
1
-C
3
define poles of the transfer function of the noise signal.
The coefficients A
1
to A
4
and C
1
to C
3
are chosen to provide circuit stability amongst other desired properties.
The coefficients C
1
-C
3
are chosen to provide noise shaping so as to minimise quantization noise in the audio band, as shown for example in
FIG. 3
by the full line
31
.
The coefficients A
1
-A
4
and C
1
-C
3
are also chosen for a desired audio signal processing characteristic.
The coefficients A
1
-A
4
and C
1
-C
3
may be chosen by:
a) finding the Z-transform H(z) of the desired filter characteristic—e.g noise shaping function; and
b) transforming H(z) to coefficients.
This may be done by the methods described in
“Theory and Practical Implementation of a Fifth Order Sigma-Delta A/D Converter, Journal of Audio Engineering Society, Volume 39, no. 7/8, 1991 July/August by R. W Adams et al.”
and in the above mentioned paper by Angus and Casey using the knowledge of the person skilled in the art. One way of choosing coefficients is outline in the attached Annex A.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a signal processor for processing 1-bit signals comprising an input for receiving a 1-bit signal having a first sampling rate, means coupled to the input for increasing the sampling rate to a second rate greater than the first rate, a plurality of 1-bit nth order Delta-Sigma Modulators (where n≧1) in series for processing the signals at the second rate, and means coupled to the stages to receive the processed 1-bit signal and to reduce the sampling rate to the first rate for output from the processor.
By increasing the sampling rate, the quantization noise power is spread over a greater band width, reducing noise in the signal band.
In addition, in an embodiment of the invention the series of DSM's are implemented on a silicon integrated circuit. By increasing the sampling rate better use is made of the frequency response of the integrated circuit in addition to spreading the quantisation noise power.
The 1-bit signal comprises samples representing +1 and −1. The increasing means or up converter may increase the sampling rate by repeating sample values or by adding zeroes to the bit stream. For example to double the sample rate each +1 is repeated once to give +1,+1 and each −1 is repeated to give −1,−1. Alternatively zeroes are provided between successive samples. Repeating sample values maintains a good approximation to the desired frequency responses and maintains signal energy. Adding zeroes maintains the frequency response but dilutes the signal energy.
The reducing means or down converte

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