Image analysis – Image compression or coding
Reexamination Certificate
1996-11-27
2001-02-13
Couso, Jose L. (Department: 2724)
Image analysis
Image compression or coding
C382S246000, C386S349000
Reexamination Certificate
active
06188791
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus and, more particularly, to instantaneous reproduction of variable-length-coded image data.
2. Description of the Related Art
An image coding apparatus for quantizing input image data and variable-length-coding the quantized image data so as to correspond to a transmission speed is conventionally known.
FIG. 1
is a block diagram showing an image coding apparatus for performing variable length coding by controlling the data amount to be generated during a next unit time T (s) in accordance with a generated data amount N [bits] per unit time T [s].
The image coding apparatus shown in
FIG. 1
comprises a quantization circuit
12
, a variable length coding circuit
13
, a buffer memory
14
, a redundancy code addition circuit
15
, and a data amount detection/control circuit
16
. Image data S
1
input from an input terminal
11
is converted into quantized data S
2
by the quantization circuit
12
. This quantized data S
2
is supplied to the variable length coding circuit
13
and is coded into data having a target data amount in accordance with a coding parameter S
3
supplied from the data amount detection/control circuit
16
.
Coded data S
4
is temporarily stored in the buffer memory
14
, and then added with an error correction code, a transmission sync signal, a control code, and the like in the redundancy code addition circuit
15
. The resultant data is output as redundancy-code-added data S
5
from an output terminal
17
.
The data amount detection/control circuit
16
outputs the coding parameter S
3
on the basis of a detection signal S
6
for detecting the amount of data stored in the buffer memory
14
and determines the target data amount of the coded data S
4
output from the variable length coding circuit
13
.
FIG. 2
is a view showing the data amount generated when the image coding apparatus in
FIG. 1
controls the generated data amount using one frame time as the unit time T [s].
For example, if data amounts generated during the frame times [s] of the first to nth frames are defined as N
1
to N
n
, [bits], respectively, the generated data amount is controlled such that m frames have a data amount which is m times a reference data amount [(total transmission amount - redundancy data amount)/frame count per second].
FIG. 2
exemplifies a case for m=3. The data amount of the first frame is N
1
[bits]; the data amount of the second frame, N
2
; and the data amount of the third frame, N
3
. As can be apparent from
FIG. 2
, when data amount control of the image data is performed as described above, the data amounts of the respective frame images are not equal to each other.
When variable-length-coded image data as described above is to be received and decoded, an implementation for reproducing the sync frequency of an image signal is required at the receiving end because the transmission clock frequency which determines the transmission speed is asynchronous with the sync frequency of the image signal.
More specifically, as shown in
FIG. 2
, a data end code (EOB) is added to the end of the image data of each frame, the EOB is detected at the receiving end, and the reproduction sync frequency at the transmitting end is reproduced in accordance with a phase-locked loop using the frame frequency as a reference.
According to this method, however, the variable range of data amount control at the transmitting end cannot be widened because limitations are imposed by the lock range of the phase-locked loop.
In above method the convergence time of the phase-locked loop is long because the frame frequency serves as a reference. Therefore, the method cannot instantaneously cope with trouble caused by the hit of a sync signal or the like.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation and has as its object to provide an image processing apparatus capable of instantaneously reproducing an image sync frequency of the transmitting end at the receiving end even if the image data amount generated in each frame greatly varies.
In order to achieve the above object, according to an aspect of the present invention, there is provided an image processing apparatus comprising input means for inputting image data, coding means for performing variable length coding of the image data input from the input means, and addition means for adding frequency information of an image sync signal of the image data to the variable-length-coded image data.
In order to achieve the above object, according to another aspect of the present invention, there is provided an image processing apparatus for reproducing variable-length-coded image data with which frequency information of an image sync signal of the image data is transmitted, comprising decoding means for decoding the variable-length-coded image data, detection means for detecting the frequency information of the transmitted image sync signal, and reproduction means for reproducing the image sync signal in accordance with an output from the detection means.
REFERENCES:
patent: 4534055 (1985-08-01), Iinuma
patent: 4603347 (1986-07-01), Kuroda
patent: 4729020 (1988-03-01), Schaphorst et al.
patent: 5109451 (1992-04-01), Aono et al.
patent: 5272528 (1993-12-01), Juri et al.
patent: 5329375 (1994-07-01), Juri et al.
patent: 5349384 (1994-09-01), Oguro
patent: 5351131 (1994-09-01), Nishino et al.
patent: 5398067 (1995-03-01), Sakamoto
Canon Kabushiki Kaisha
Couso Jose L.
Do Anh Hong
Fitzpatrick ,Cella, Harper & Scinto
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