Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1998-05-15

2001-10-09

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050

Reexamination Certificate

active

06301158

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, more specifically to a flash EEPROM in which a memory cell is made of an MOSFET comprising both a floating gate and a control gate, and data is stored based on the amount of charges stored in the floating gate. In particular, the present invention is directed to a virtual grounded type flash EEPROM.
This application is based on Japanese Patent Application No. 9-126137, filed May 16, 1997, the content of which is incorporated herein by reference.
FIG. 1
shows the memory cell array of a conventional flash EEPROM.
FIG. 2A
is a plan view showing part of the memory cell array depicted in
FIG. 1
, and
FIG. 2B
is a sectional view taken along line
2
B—
2
B in FIG.
2
A. In
FIG. 2B
, illustration of an oxide film is omitted.
In the conventional flash EEPROM shown in FIG.
1
and
FIGS. 2A and 2B
, data is written in a memory cell by applying a high voltage to a word line (row line) WL and a bit line (column line) BL and applying a reference potential (e.g., a ground potential) to the common source VSS of memory cells. Since, therefore, a current is allowed to flow through the memory cell, charges are injected in the floating gate. When data is erased from the memory cell, charges are injected in the floating gates of all memory cells. After the floating gates of all memory cells are thereby set in a uniform state, all word lines are set at the reference potential level. In this state, a high voltage is applied to the common source VSS of the memory cells, and charges are thereby made to emit from the floating gates to the source by utilization of a tunnel effect, thereby erasing data from the memory cell.
In this type of EEPROM, the bit lines BL are formed of aluminum, and the drain regions of adjacent two memory cells are commonly connected to the bit line. Due to this structure, the area used for connection is inevitably wide and gives rise to a low manufacturing yield.
In consideration of the above circumstances, flash EEPROMs having a virtual grounded structure are under development.
FIG. 3
shows the memory cell array of such a flash EEPROM.
FIG. 4A
is a plan view showing part of the memory cell array shown in
FIG. 3
, and
FIG. 4B
is a sectional view taken along line
4
B—
4
B in FIG.
4
A.
In the EEPROM having a virtual grounded structure, N
+
regions, used as sources and drains of memory cells, are connected to bit lines BL
1
-BL
9
(i.e., column lines). Since the bit lines BL
1
to BL
9
are formed in those N
+
regions which are under control gates CG, it is not necessary to provide a connection element to connect the bit lines BL
1
-BL
9
and the memory cells
11
-
88
together, unlike the memory cells shown in
FIGS. 2A and 2B
. Accordingly, the memory cell area can be reduced, and the connection between the bit lines and memory cells does not lower the manufacturing yield.
A description will now be given as to how data is written in a memory cell of the EEPROM of a virtual grounded structure, with charges stored in the floating gate of the memory cell. By way of example, let us consider the case where data is written in memory cell
12
. In this case, a high voltage is applied to both word line WL
1
(i.e., a row line) and bit line BL
2
, thereby setting bit line BL
3
at a reference potential level (e.g., a ground potential level). In this state, a current flows through the memory cell
12
, thus permitting the floating gate to store charges. Although the bit line BL
1
is in the electrically floated condition at the time, the memory cell
11
is turned on due to the high voltage applied to the word line WL
1
. Since the high voltage is applied to the bit line BL
2
, the bit line BL
1
is charged through the memory cell
11
in an amount corresponding to the parasitic capacitance of the bit line BL
1
. In order to prevent the floating gate of the memory cell
11
to store charges in spite of the charged state of the bit line BL
1
, an offset transistor T
off
is provided for each of the memory cells, as shown in FIG.
4
B. The offset transistor T
off
has its channel portion controlled by the control gate CG. Even when data is written in the memory cell
12
, the offset transistor T
off
connected to the bit line BL
2
to which a high voltage is applied, serves to prevent the floating gate FG of the memory cell
11
from storing charges.
At the same time, however, the use of the offset transistor T
off
inevitably increases the memory cell size because the offset transistor T
off
is incorporated in the memory cell.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device of a virtual grounded type, which does not comprise a connection element to connect the bit lines and memory cells, and which further eliminates the need to provide an offset transistor for each memory cell.
Another object of the present invention is to provide a novel method for writing data in a memory cell of a nonvolatile semiconductor memory device of a virtual grounded type.
According to the first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a plurality of word lines; a plurality of bit lines; a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells including a charge storage layer, a control gate, a drain, a source, and a channel region, and storing data based on the amount of charges stored in the charge storage layer, the control gates of the memory cells of one row are connected to one of the word lines, adjacent ones of the memory cells of one row being connected such that the drain of one of the adjacent ones is connected to the source of the other, adjacent ones of the memory cells of one column being connected such that the drain of one of the adjacent ones and the source of the other are connected to one of the bit lines; a row decoder, supplied with an address signal, for selecting one of the word lines; a column decoder, supplied with an address signal, for selecting one of the bit lines; and a program circuit for programming data in the memory cells, the program circuit executing data programming such that data programming for the memory cells of one column is completed first and then data programming for the memory cells of an adjacent column is started, and such that data programming makes progress from the memory cells at one end of the memory cell array to the memory cells at the other end of the memory cell array.
In the manner described above, the programming for the memory cell array is executed, first with respect to the memory cells corresponding to the bit line at one end, and makes progress from that bit line to the adjacent one. When the memory cells corresponding to the adjacent bit line are being programmed, it is possible to prevent data from being mistakenly written in the memory cells corresponding to the bit line arranged at the end. Accordingly, it is not necessary to connect offset transistors.
According to the nonvolatile semiconductor memory device of the second aspect of the present invention which is a modification of the first aspect, the row decoder receives program data to be written in the memory cells, a high voltage is applied to the word line selected in accordance with an address signal such that the voltage application is based on the program data, and control is executed whether or not to permit the charge storage layer to store charges.
Owing to this feature, a high voltage can be applied to a word line corresponding to a memory cell in which data “1” is written.
According to the nonvolatile semiconductor memory device of the third aspect of the present invention which is a modification of the first or second aspect, there is further provided a column selecting circuit that causes the row decoder to control the connection between the bit lines and the program circuit. Assuming that the adjacent three bit lines are arranged in the order of a fir

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