Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2000-06-08
2001-12-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C438S199000, C438S217000, C438S224000, C438S228000
Reexamination Certificate
active
06329218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a sensor, and more particularly, to a method for forming a CMOS sensor where the ion implantation within the regions of field isolation of the sensor photo-diode array is implemented separately from the ion implantation within NMOS.
2. Description of the Prior Art
Integrating photocell area-array image sensors with signal processing circuits on one chip using complementary metal oxide semiconductor (CMOS) technology is currently under heavy development for emerging multimedia applications. Presentations on this topic were included in the IEEE ISSCC conferences of '96 and'97. A variety of methods are used to form semiconductor image sensors on a substrate with CMOS devices.
The traditional process for image sensor fabrication is simultaneously completed with NMOS. As shown in
FIG. 1
, for a CMOS sensor consisting of the portions of sensor photo-diode array
5
, NMOS
7
and PMOS
9
, a semiconductor structure is provided with a semiconductor layer
100
, P-epitaxial layer
110
, P-well
130
, N-well
120
and gate structure
150
. A plurality of field regions
140
of sensor photo-diode array, bounded with P-well, are formed simultaneously with a source/drain
160
of NMOS. Thus, such a fabrication results in high impurity concentration within the region of sensor photo-diode array and the doses of ion implantation within the region of the sensor photo-diode array are as high as ones within NMOS.
However, in the region of the sensor photo-diode array, a junction that collects carriers induced by incident light, forming in a highly doped region, will result in a large capacitance. That is, the large capacitance reduces the amount of charge that can be transferred from the photo sensing element to other electronics and the detection sensitivity decreases. Furthermore, because of higher dose of field region within the region of sensor photo-diode array, it is difficult to meet the requirements of isolation and low dark current required for the image sensor.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a CMOS image sensor. In the present invention, partial steps involving implantation for image sensor fabrication are implemented at different time with fabrication of NMOS. The present invention is compatible with the present process only to add a mask for patterning sensor implantation and to modify some of the traditional patterns of masks.
It is another object of the present invention to provide a method for fabricating a CMOS image sensor with a high ratio of S/N (sensitivity/dark current). The doses of the field region within the region of sensor photo-diode array can be implemented separately and are not subject to higher dopants for NMOS in present fabrication. Thus, the doses for the sensor photo-diode array can be adjusted to meet the requirements of isolation and low dark current for image sensor and a CMOS image sensor with high ratio of S/N can be implemented.
In one embodiment, a method for forming CMOS image sensor is disclosed. The method includes providing a semiconductor structure that comprises of a P-epitaxial layer on a P-type substrate. The semiconductor structure has a sensor photocell array. NMOS and PMOS. Firstly, the P-type ion is implanted into the P-epitaxial layer to form a P-well of NMOS and a plurality of isolation P-wells as isolation devides for the sensor photocell array. The N-type ion is then implanted into the P-epitaxial layer to form an N-well of PMOS and then the wells of two types are profiled by the method of drive-in. A plurality of isolation regions are formed on the surface of the P-epitaxial layer by a conventional method such as local-oxide silicon. The P-type ion is implanted into P-well of NMOS and thereafter a field channel stop and an anti-punchthrough channel are formed in P-well of NMOS. Next, a threshold voltage of CMOS is adjusted by blanket implantation of P-type ions. A plurality of gate structures that comprises a gate oxide layer and a polysilicon layer are formed on the surface of NMOS and PMOS. THe N-type ion is implanted into P-well to form LDD region of NMOS and PMOS. the N-type ion is implanted into P-well to form LDD region of NMOS and P-type ion is implanted into N-well to form LDD region of PMOS. Then a plurality of spacers are formed on the side wall of gate structures of NMOS and PMOS by the suitable methods. in P-well and N-well, the source/drain regions are formed by the individual implantation of N-type and P-type ion. The impurity concentration in LDD regions is lower than that in source/drain regions. Then the key step forming field isolation in the sensor photocell array is in the ion implantation within the sensor photocell array at a dose of approximately 1E12 to 1E13 atoms/cm2 that can both reduce the leakage and dark current of said sensor photocell array. Finally, by using the same implanting mask for forming the field isolation, the field regions in the sensor photo-diode array are implemented by N-type retrograde implantation that can reduce the peak effect around the corner of the isolation region in the sensor photocell array and simultaneously add the area of collecting incident light.
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Luu Chuong A
Smith Matthew
United Microelectronics Corp.
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