Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-06-25
2001-11-20
Chin, Wellington (Department: 2664)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S509000, C370S515000, C370S516000, C375S357000, C375S373000, C375S376000
Reexamination Certificate
active
06320881
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to counters and tracking protocols generally and, more particularly, to a method, architecture and circuit for locking a data transmission frame.
BACKGROUND OF THE INVENTION
In a universal serial bus (USB) protocol, a start of frame (SOF) packet is transmitted once every 12,000±45 bit times. A full speed USB device (as opposed to a low speed USB device) must track this SOF packet to ensure a period is within two bit times of the previous period. The USB protocol allows for two SOF packets to be missed. However, if a third packet is missed, the device is not locked and may not properly respond to USB traffic.
One conventional approach for implementing such a mechanism would be to implement an arithmetic incremental counter with a memory used to store the previous frame period and an arithmetic, subtractive comparator to decoder whether the frame period was within an acceptable time length. In addition, since a SOF indicator may be missed, the second counter is needed to start counting the period in the frame from the point at which it was expected to start. In addition, the second count value must be loaded into the main counter at some point during the frame count.
The overall operation is controlled by the decoder, which keeps track of whether the device is locked to the SOF signal or not. The decoder must also decode the range of allowable occurrences of the SOF signal and then use this information to control the counters and the count memory. Since several such ranges are needed to perform all of this control functionality, multiple comparators would be required. The standard method requires arithmetic functions, specifically incrementors and comparators, which are large and slow.
Referring to
FIG. 1
, a circuit
10
is shown illustrating a conventional method of tracking a SOF packet. The circuit
10
generally comprises a main counter
12
, a frame period memory
14
, a decoder
16
, and a secondary counter
18
. The main counter
12
has an output
20
that may present a multi-bit signal MAINCOUNT to an input
22
of the decoder
16
as well as to an input
24
of the frame period memory
14
. The decoder
16
has an output
24
that presents a signal LOADMAINCOUNT back to an input
26
of the main counter
12
. The SOF signal is generally presented to an input
17
of the decoder
16
. The decoder
16
also has an output
28
that presents a signal that may indicate when the tracker is locked to the host transmitter via the SOF indicator, an output
30
that presents a signal STARTSECONDARYCOUNT to an input
32
of the secondary counter
18
and an output
32
that presents a signal to an input
34
of the frame period memory
14
that indicates when the memory should be updated. The frame period memory
14
also has an output
36
that may present a multi-bit signal FRAMEPERIOD [
13
:
00
] to an input
38
of the decoder. The secondary counter
18
has an output
40
that may present a multi-bit signal SECONDARYCOUNT [
13
:
00
] to an input
42
of the main counter
12
.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a first counter, a second counter, a third counter and a decoder, where the decoder may be configured to present a locked output signal. The first counter may present a first output signal in response to a start of frame signal and one or more control signals. The second counter may be configured to present a second output signal in response to the start of frame signal and the first output signal. The third counter may present a tracking control signal to the first counter in response to one or more of the control signals.
The objects, features and advantages of the present invention include providing a SOF tracker that (i) may implement LSFR counters to simplify counting and decoding, (ii) may be implemented using less logic which may result in faster circuits using less area, (iii) may allow the implementation of decoders rather than comparators, and (iv) may replace a memory with a smaller tracking counter.
REFERENCES:
patent: 4577319 (1986-03-01), Takeuchi
patent: 4641326 (1987-02-01), Tomisawa
patent: 4979192 (1990-12-01), Shimizume et al.
patent: 5410571 (1995-04-01), Yonekawa et al.
patent: 5483558 (1996-01-01), Leon et al.
patent: 5570394 (1996-10-01), Tsurumaki
patent: 5576665 (1996-11-01), Erhage
patent: 5675813 (1997-10-01), Holmdahl
patent: 9736230 (1997-10-01), None
Universal Serial Bus Specification, Chapter 7—Electrical, Jan. 15, 1996, pp. 111-143.
Chin Wellington
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Phan M.
LandOfFree
Method, architecture and circuit for locking a data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, architecture and circuit for locking a data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, architecture and circuit for locking a data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2581828