Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1998-02-26
2001-02-27
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S735000, C257S686000, C257S737000, C257S778000, C257S781000, C228S180220
Reexamination Certificate
active
06195268
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the stacking of layers containing IC chips, therby obtaining high density electronic circuitry. In general, the goal of the present invention is to combine high circuit density with reasonable cost. Cost reduction involves (a) relatively low cost initial forming of layers, (b) ability to use simple layer-testing techniques, and (c) effective ways of guaranteeing that defective layers will not be included in the stacks.
Another aspect of successful stacking of chip-containing layers is the availability of large numbers of input/output (I/O) terminals (or pads) for connecting the stack to external circuitry.
In most of the extensive prior art disclosures, the leads from the chip-embedded IC circuitry are brought out at one or more sides of the stack, i.e., at the periphery of the stacked layers. Some packages bring conductors from the IC circuitry through vertical vias extending to the bottom of the package, permitting the use of I/O pads on the bottom of the package, i.e., ball grid arrays of terminals on a single flat surface.
Hayden et al U.S. Pat. No. 5,579,207 shows a structure in which stacked chip-enclosing layers have vertically-extending vias serving as conductors between the IC chips and a plurality of pads on the top and bottom of the stack. Each layer substrate (chip carrier) in the Hayden et al patent has an IC chip mounted on its upper surface, and a cavity formed in its lower surface, which provides space for the IC chip on the layer below. The layers are separately formed and then stacked, using flat sealing strips around the peripheral edge between adjacent layers to provide sealing of the cavities, i.e., sealing occurs as a result of stacking. Because the Hayden et al patent extends the IC chip mounted on one carrier into the cavity of the next carrier, it is not possible to pretest the individual carriers as sealed, or covered, units.
What is not available in the prior art is a stack of IC-chip-containing layers which can be fully tested individually prior to stacking, and can connect the chip circuitry through vias to a ball grid array at the bottom of the stack, which array may if desired have terminals located at points throughout the full planar surface.
SUMMARY OF THE INVENTION
This application discloses two versions of fully pre-testable chip-containing layers, which can be stacked and have the chips electrically connected to a ball grid array on the bottom of the stack. One version, which is hermetically sealed, uses ceramic as the dielectric body material which provides the chip-containing cavity in each layer. The other version uses polyimide as the dielectric body material which provides the chip-containing cavity in each layer. In each version the individual layers are proved to be “known good” parts before stacking.
In each version, the dielectric layer material is laminated, so that electrical conductors (traces) can extend horizontally inside the dielectric material and be connected by wire bonding to I/O terminals on the chip die. Vias containing vertical conductors are formed in each stacked layer, which vias extend from top to bottom of the layer and intersect the appropriate horizontal traces. The vias also provide electrical conduction to an array of terminals located on the bottom of one layer, which terminals engage aligned terminals located on the top of the next layer.
Each layer is completed and enclosed before stacking, with the IC chip or chips inside the cavity, and covered on top either by a lid in a ceramic layer, or by epoxy which fills the cavity of a polyimide layer. Therefore, in order to provide good stack test yields and stack integrity, each enclosed chip may be conventionally tested and prepared prior to stacking of the layers, including:
(a) Tested at extreme temperatures (e.g., minus 55° C., plus 125° C.);
(b) Burned in (both temperature and bias); and
(c) Environmentally screened (i.e., temperature cycle, thermal shock, humidity, bias).
If necessary, because the stack consists of completed IC packages, the stack can be conventionally reworked to remove defective layers, without compromising the integrity of the IC chips themselves.
The availability of the full bottom surface of the stack for terminals, and the virtually unlimited vertical interconnections, allow for a very high input/output (I/O) count accommodate the needs of the stacked ICs.
REFERENCES:
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 5060844 (1991-10-01), Behun
patent: 5291062 (1994-03-01), Higgins, III
patent: 5311402 (1994-05-01), Kobayashi et al.
patent: 5376825 (1994-12-01), Tukamoto et al.
patent: 5550403 (1996-08-01), Carichner
patent: 5550408 (1996-08-01), Kunitomo et al.
patent: 5579207 (1996-11-01), Hayden et al.
patent: 5600541 (1997-02-01), Bone et al.
patent: 5701233 (1997-12-01), Caarson et al.
patent: 5783870 (1998-07-01), Mostafazadeh et al.
patent: 5923540 (1999-07-01), Asada et al.
patent: 5956233 (1999-09-01), Yew et al.
patent: 6002170 (1999-12-01), Kim et al.
patent: 6043430 (2000-03-01), Chun
patent: 6064120 (2000-05-01), Cobbley et al.
patent: 03-034445 (1991-02-01), None
Andras Joseph C.
Gaffin Jeffrey
Myers Dawes & Andras
Vigushin John B.
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