Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-10-20
2001-11-27
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S199000, C438S224000
Reexamination Certificate
active
06323103
ABSTRACT:
BACKGROUND
This invention relates to methods for fabricating transistors, namely complementary metal-oxide field effect transistors (CMOS FETS).
The cost and yield of a fabricating process for fabricating semiconductor chips depends on various factors. One factor is the number of masks (or masking layers) which are used during the process. An increase in the number of masks used in a process generally increases the cost of the process. Another factor is the extent to which the process uses self-aligned processing steps or misalignment tolerant structures. Misalignment tolerant structures are structures which, when being fabricated, have a high degree of tolerance to being misaligned with previously formed or subsequently formed structures. As is obvious, self-aligned steps or misalignment tolerant structures increase the yield of the fabricating process by reducing the number of chips which are inoperative due to misalignment. Therefore, it is generally preferable to reduce the number of masks and to increase the number of self-aligned steps and misalignment tolerant structures used in a manufacturing process. However, these two objectives must also be balanced against one another and against the features desired in a process.
Consider an exemplary DRAM memory chip. In such a DRAM memory chip, various types of logic circuits provide various functions. For example, address decoders decode address lines and access DRAM cells in a memory array, clock generators generate and process various clock signals, and refresher circuits refresh the DRAM cells in the memory array. Unlike the DRAM cells in the memory array which are implemented by a single type of metal oxide semiconductor field effect transistor (MOSFET or FET), the logic circuits in such a DRAM memory chip are typically implemented by complementary MOS FETs (CMOS FETs), which include both n-type and p-type FETs (n-FET or p-FET, respectively).
One desirable feature in a CMOS circuit is for the circuit to be a dual work function circuit. In such a circuit, the gate electrode of the n-FET transistors and the p-FET transistors are fabricated differently from one another so that they may be optimized for low work function. Since a transistor with lesser work function uses a lower voltage level than one with a higher work function, the former transistor uses lower power and may be fabricated to have smaller dimensions and faster switching speeds.
To understand such a dual work function circuit, consider an n-FET or p-FET transistor. As is well known, the gate electrode of such a transistor is made up of at least a gate oxide and a gate conductor. The gate conductor is typically a doped poly-crystalline silicon (also known as polysilicon) layer. If the gate poly-crystalline silicon layer of an n-FET or p-FET is doped with the opposite type of dopant as the channel region below the gate electrode, the work function of the gate is less than when the gate poly-crystalline silicon layer is doped with the same type of dopant. However, the channel region of a CMOS transistor may be either n-doped or p-doped silicon based on whether the CMOS transistor is a p-FET or n-FET. Therefore, to provide for optimal work function in a CMOS circuit, the gate poly-crystalline silicon layer of n-FETs should be n-doped while the gate poly-crystalline silicon layer of p-FETs should be p-doped. Such a CMOS circuit then provides for dual-work functions.
Another desirable feature in integrated circuits is the ability to use so-called “border-less” contacts, since borderless contacts have a higher degree of misalignment tolerance and allow an increased number of transistors per unit of area. Borderless contacts also reduce the possibility of a short circuit between the contact and the gate electrode. To form borderless contacts, the gate electrode is covered, in its relevant parts, by dielectric barriers. The dielectric barriers are typically a dielectric cap on the top surface of the gate electrode and dielectric spacers on the sides of the gate electrode where the contact is to be formed. Because these dielectric barriers insulate the gate electrode, there is a low probability of misalignments causing short circuits between the contact and the gate electrode.
SUMMARY
In accordance with one feature of the invention, the invention features a method for fabricating first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body. Each one of the transistors has a plurality of layers. A first layer is formed over the active areas. A mask is then provided over the first active area, such mask defining an opening coextensive with the second active area. Material is deposited through the opening to form a second layer and a third layer, such second and third layers being coextensive with the second active area. The first transistor is formed with the first layer as one of the plurality of layers of such first transistor and the second transistor is formed with the second layer and third layer as a pair of the plurality of layers of the second transistor.
Accordingly, a single mask may be used to deposit at least two layers to become part of the second transistor. Therefore, in some embodiments where, for example, it is necessary to remove the gate oxide and/or gate control layer in an active area and to form a new gate oxide or gate control layer, the same mask may be used to implant a doped well as one layer and deposit the gate oxide and/or gate control layers as another layer.
In accordance with another feature of the invention, the first layer is formed in both the first and second active areas and then removed in whole or in part the first layer from the second active area. The first layer may be a first gate oxide layer. A first poly-crystalline silicon layer may also be deposited, the first poly-crystalline silicon layer being one of the plurality of layers of the first transistor. In that case, the mask covers the first poly-crystalline silicon layer. The second layer may be a second gate oxide layer and the third layer a second poly-crystalline silicon layer. One of the first and second poly-crystalline silicon layers may be an n-doped poly-crystalline silicon layer and the other one of the first and second poly-crystalline silicon layers a p-doped poly-crystalline silicon layer. The first gate oxide layer and the second gate oxide layer in turn may have different thicknesses.
In accordance with still another feature of the invention, the semiconductor body has a first type of dopant and the material includes a second type of dopant forming a doped well in the semiconductor body, the second layer being the doped well.
In accordance with another feature of the invention, trenches are etched in the first gate oxide and poly-crystalline silicon layers, and also in the semiconductor body, to delineate the first and second active areas. A first delineated gate oxide and poly-crystalline silicon layers coextensive with the first active area are thereby formed. Material is then deposited in the trenches to form the active area isolations, the active area isolations having a top surface above the semiconductor body. Active area isolations define the second active area and electrically isolate the second active area. A masking layer over the first and second active areas is formed and selective portions of it are removed to expose the second active area. The active area isolations are part of the mask and in part or in whole define the opening.
In accordance with another feature of the invention, material is deposited to form a fourth layer over the mask covering the first active area and in the second active area, selected portions of the fourth layer are then removed to form one of the second and third layers. Portions of the fourth layer are removed by using a chemical mechanical polish (CMP) process to etch the fourth layer until the fourth layer is at the same level or below the top surface of the active area isolations.
In accordance with yet another feature of the invention, the second transistor is formed by
Beintner Jochen
Gruening Ulrike
Joachim Hans-Oliver
Rengarajan Rajesh
Fourson George
Pham Thanh V
Siemens Aktiengesellschaft
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