Successive approximation analog-to-digital converter circuit

Details Successive approximation analog-to-digital converter circuit Successive approximation analog-to-digital converter circuit

2000-01-19

2001-10-16

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S163000

Reexamination Certificate

active

06304208

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an analog-to-digital converter circuit capable to being included in a semiconductor integrate circuit. More specifically, the present invention relates to a successive approximation mation analog-to-digital converter circuit capable being operated at a high speed with high accuracy.
The successive approximation analog-to-digital converter circuit conventionally used has a digital-to-analog conversion circuit, which is formed of a resistor string in which a plurality of resistors are connected in series, as a reference voltage generation circuit. Hereinafter, the resistor string will be referred to as “resistor circuit” and the digital-to-analog conversion to “D/A conversion”.
In this case, if a parasitic resistance is present at electrode portions of both ends of the resistor circuit, the parasitic resistance has an effect upon the voltage between intermediate terminals of the resistor circuit, in other words, a reference voltage generated at both ends of a unit resistor constituting the resistor circuit, with the result that the resultant voltage is smaller than normally obtained. Therefore, the D/A conversion code converted from an analogous input voltage by using the D/A conversion circuit includes an error corresponding to a voltage drop due to the parasitic resistance.
To avoid the decrease in conversion accuracy due to the parasitic resistance, it may be considered that the resistance of the resistor circuit constituting the D/A conversion circuit is increased. However, the high resistance is a big drawback to attaining the high speed conversion. Alternatively, it may be considered that resistances of unit resistors corresponding to the most significant and least significant sides of the resistor circuit are lowered in consideration of the parasitic resistance. However, since the resistances vary depending upon variation of process conditions, it is extremely difficult to set the resistances accurately.
Now, referring to
FIG. 1
, problems of the conventionally-used D/A conversion circuit will be explained in detail.
The DAC block shown in the leftmost column of
FIG. 1
indicates a resistor circuit constituted of a plurality of unit resistors connected in series. The DAC block is a main constitutional element of the D/A conversion circuit generating a reference voltage for determining the D/A conversion code.
However, in practice, parasitic resistances R
L
, R
H
are present respectively between the DAC block and each of two end terminals of the DAC block, one for applying a reference voltage (generating a reference voltage) V
REFL
at a low voltage side and the other for applying a reference voltage V
REFH
at a high voltage side.
FIG. 1
(at the upper right portion) schematically shows the relationship between the potential distribution V
dac
of the D/A conversion circuit (mainly composed of the DAC block having parasitic resistances at both ends) and the A/D conversion code determined by using the potential distribution. Note that “00H” and “FFH” plotted on the longitudinal axis are the A/D conversion code in terms of hexadecimal notation. A broken line indicates the case where the parasitic resistances R
L
, R
H
are absent. The solid line corresponds to the case where the parasitic resistances are present.
As shown in the graph, when the parasitic resistances are absent, a simple proportional relationship is established between the potential distribution V
dac
and the A/D conversion code. Whereas, when the parasitic resistances are present, a voltage drop due to the presence of the parasitic resistances R
L
, R
H
has an effect upon both ends of the potential distribution. Since the A/D conversion code is determined based upon the potential distribution, an error is included. Since the graph is drawn assuming that R
L
is equal to R
H
, an error is not presented in the middle of the graph. However, since R
L
is not equal to R
H
in practice, the solid line shown in the graph is evenly (equally) deviated from the broken line (hereinafter, referred to “off-set error”).
If a product obtained by multiplying a theoretical value of the A/D conversion code obtained on the basis of the case without the parasitic resistance by a voltage of the least significant bit, is represented by V
DAC
, an analogous input voltage input into the analog-to-digital circuit is represented by V
AIN
, and an overall conversion error is represented by V
err
=V
dac
−V
AIN
, V
dac
>V
DAC
at the low voltage side, and V
dac
<V
DAC
at the high voltage side are obtained as shown in
FIG. 1
, at a lower right side. To obtain a correct code, V
dac
must be reduced at the low voltage side of the DAC block and V
dac
must be increased at the high voltage side.
Referring now to
FIG. 2
, operation of the successive approximation A/D converter circuit conventionally used will be schematically explained. The successive approximation A/D converter circuit shown in
FIG. 2
is constituted of a voltage comparing circuit
1
, a D/A conversion circuit
4
, and an A/D conversion control circuit
5
.
To the successive approximation A/D converter circuit, an analogous input voltage V
AIN
is input. The D/A conversion circuit
4
outputs the voltage V
dac
D/A-converted from the DAC block. The voltage comparing circuit
1
compares the analogous input voltage V
AIN
with the D/A converted voltage V
dac
. The A/D conversion control circuit
5
has a register circuit for determining and holding a predetermined data corresponding to one-bit of the D/A conversion code depending upon the output from the voltage comparing circuit
1
.
The A/D conversion control circuit
5
repeats the comparing/determining operation per bit from the most significant bit (MSB) to the least significant bit (LSB) of the D/A conversion code. The D/A conversion code finally determined, in other words, a DAC code
5
a
shown in
FIG. 2
, is output to the D/A conversion circuit
4
. In this manner, the D/A conversion code is held in a register circuit as an A/D conversion data.
To explain more specifically, the successive approximation A/D converter circuit comprises a sample-hold condenser C
SH
connected to one of input terminals of the voltage comparing circuit
1
, a reference condenser C
ref
connected to the other input terminal of the voltage comparing circuit
1
, a switch SW
SH
connected to one of the terminals of the sample-hold condenser C
SH
, for switching the analogous input voltage V
AIN
and the D/A converted voltage V
dac
from each other, and switches SW
AZN
, SW
0
, SW
AZP
directly connected to the sample-hold condenser C
SH
and the reference condenser C
ref
by bypassing the voltage comparing circuit
1
. The switches SW
AZN
, SW
0
, SW
AZP
are simultaneously turned on during a sample-hold period.
An arrow of the broken line
3
indicates that a plurality of switches are operated in connection with each other between the sample-hold period and the period (hereinafter, referred to as “comparing period”) in which V
AIN
and V
dac
are compared with each other in the voltage comparing circuit
1
, as in the aforementioned manner.
In the sample-hold period, the switch SW
SH
is connected to a V
AIN
side. Simultaneously, the switches SW
AZN
, SW
0
, SW
AZP
are turned on and C
SH
, and C
ref
are connected in series. As a result, the C
SH
, and C
ref
are rapidly charged with a potential difference between V
AIN
and V
REFH
.
When the sample-hold operation by the sample-hold condenser C
SH
is completed, the switches SW
AZN
, SW
0
, SW
AZP
are turned off, whereby the bypass of the voltage comparing circuit
1
is opened and the voltage comparing circuit
1
becomes active. As a result, voltage V
opn
and V
opp
(V
opn
) obtained before the opening are maintained at the differential input.
More specifically, the sample-hold voltage of the analogous input voltage V
AIN
is transferred to + input voltage V
opp
of the voltage comparing circuit
1
by the switching operation, and maintained by C
ref
over the comparing periods sequentia

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