Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
1999-07-21
2001-12-04
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S191000, C703S013000, C716S030000, C716S030000
Reexamination Certificate
active
06327542
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer-aided circuit design systems, and more particularly to a system and method for evaluating a netlist file and approximating the coupling voltage noise on a node
2. Discussion of the Related Art
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor “chip” in which the components are interconnected to perform a given function such as a microprocessor, programmable logic device (PLD), electrically erasable programmable memory (EEPROM), random access memory (RAM), operational amplifier, or voltage regulator. A circuit designer typically designs the integrated circuit by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and ensure performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated, electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A “netlist” is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
An integrated circuit design can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a
1
hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions or a mix of both. At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are full adders, NAND gates, latches, and D-Flip Flops.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc. (purchased by Synopsys). PathMill is a transistor based analysis tool used to find critical paths and verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various circuit characteristics, attributes, or configurations that are not identified and/or addressed in the PathMill product and other similar products. For example, there is often a need to evaluate a circuit to detect a wide variety of potential design or layout pitfalls. One potential circuit pitfall relates to cross-talk (also referred to sometimes as cross-coupling or capacitive coupling) between signal lines. Specifically, in the design of VLSI chips, cross-talk may occur in deep, submicrometer interconnect systems.
Circuit simulations, such as SPICE, are known to provide the ability to analyze a circuit design and layout for cross-talk. However, the extraction tool and analysis performed by SPICE is extremely detailed and involved. At the chip level, an extraction file may be on the order of gigabytes, and the run-time required for simulation may take several weeks.
Therefore, it would be desirable to provided an automated tool that can evaluate a netlist file of a large circuit design to identify particular circuit to closely approximate the capacitive coupling between signals (or the capacitive coupling on a particular circuit node) in a very efficient manner.
SUMMARY OF THE INVENTION
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The present invention is generally directed to a system and method for approximating the coupling voltage noise on a node in a circuit and determining whether the coupling voltage noise exceeds a permissible value. In accordance with one aspect of the invention, a method uses a first circuit model to obtain a total resistance value of a conductor extending between a driver configured to drive the node and a receiver, and uses a second circuit model to determine a total capacitance. The method also determines an aggressor coupling capacitance between the node and an aggressor signal using at least one criteria, and computes a ground capacitance by subtracting the aggressor coupling capacitance from the total capacitance. The method also determines the effective resistance of the driver, and a weighted average rise time for all aggressor signals on the node. Using a third circuit model, with the values determined above, the method simulates the third circuit model to determine whether the coupling voltage noise on the node exceeds a predetermined value.
DESCRIPTION OF THE DRAWINGS
The accompanying drawings incorporated in and forming a part of the specification, illustrate several aspects of the present invention, and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1
is a block diagram of a static timing analyzer system, as is known in the prior art;
FIG. 2
is a block diagram illustrating the orientation of the electrical rules checking method of the present invention, in relation to an existing static timing analyzer;
FIG. 3A
is a top-view of a portion of a trace layout within an integrated circuit, illustrating closely disposed traces;
FIG. 3B
is a cross sectional view taken substantially along line
3
B—
3
B of
FIG. 3A
;
FIG. 4
is a schematic diagram illustrating a circuit equivalent to the trace portions illustrated in
FIGS. 3A and 3B
;
FIG. 5
is a circuit model utilized by the system and method of the present invention;
FIG. 6A
is a first circuit model utilized by the preferred embodiment of the present in
Bui Bryan
Hewlett--Packard Company
Wachsman Hal
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