Apparatus for hierarchical encoding of digital image signals...

Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal

Reexamination Certificate

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C382S232000

Reexamination Certificate

active

06320910

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an hierarchical encoding apparatus which divides a digital image signal into a plurality of signals that represent images having different respective resolutions, and encodes such signals for transmission. The invention also relates to a corresponding hierarchical decoding apparatus.
2. Description of Related Art
There has been proposed a digital image signal encoding technique in which a high resolution image signal is received as a first hierarchical image signal, a second hierarchical image signal having a lower resolution than the first signal is formed therefrom, a third hierarchical image signal having a lower resolution than the second is formed, and so forth. This technique is referred to as a hierarchical encoding technique. According to this technique, a plurality of hierarchical image signals are transmitted through a single transmission path (one communication channel or one recording and reproducing process). on the receiving side, the transmitted image data can be reproduced by a television monitor corresponding to any one of the hierarchical levels.
More specifically, it is known to use video signals having various degrees of resolution, such as standard resolution, high resolution, and low resolution. Conventional television signals are an example of standard resolution video signals. High definition television signals are an example of high resolution video signals. Low resolution video signals may be used, for example, to retrieve image data at high speed from an image data base and to display the same on a computer display. The hierarchical encoding technique may be used for enlargement and reduction of images, as well as for providing video signals of varying degrees of resolution. Hierarchical encoding may be applied to reduction of images without changing the level of resolution.
FIG. 8
illustrates an example of an apparatus which carries out the above-described hierarchical encoding technique. According to this example, the apparatus outputs three levels of hierarchical signals, with the number of pixels in the second hierarchical image signal being one-quarter of the number of pixels in the first hierarchical image signal and the number of pixels in the third (highest) hierarchical image signal being one-sixteenth of the number of pixels in the first hierarchical image signal. As shown in
FIG. 8
, an input digital image signal, corresponding to the first hierarchical signal, is provided at an input terminal
41
. The input signal is supplied from the input terminal
41
to a thin-out circuit
42
and a subtracting circuit
43
. The output of the thin-out circuit
42
is provided to an encoding circuit
45
through another thin-out circuit
44
. The output of the encoding circuit
45
is provided at a third hierarchical output terminal
53
. The thin-out circuits
42
and
44
each reduce the number of pixels in the input signal supplied thereto by one half in both of the horizontal and vertical directions. Thus, the number of pixels in the output signal of each of the thin-out circuits
42
and
44
is one-quarter of the number of pixels in the respective input signal for those circuits. Accordingly, the number of pixels in the output signal of the thin-out circuit
44
is one-sixteenth of the number of pixels in the input signal for the thin-out circuit
42
.
The encoding circuit
45
encodes the signal output from the thin-out circuit
44
and provides a resulting encoded signal to the output terminal
53
. Typically, the thin-out circuits
42
and
44
are formed of thin-out filters.
In addition, the signal output from the thin-out circuit
42
is supplied to an interpolating circuit
46
and a subtracting circuit
47
. The interpolating circuit
46
performs interpolation to supply pixels that have been thinned out by the thin-out circuit
42
. The output signal from the interpolating circuit
46
is supplied to the subtracting circuit
43
, which calculates the difference, pixel by pixel, between the input image signal provided at input terminal
41
and the output signal from the interpolating circuit
46
. The resulting differential signal is supplied from the subtracting circuit
43
to an encoding circuit
48
, which is, in turn, connected to provide an encoded output signal to a first hierarchical output terminal
51
.
The output signal from the thin-out circuit
44
is supplied to a subtracting circuit
47
by way of an interpolating circuit
49
. In a similar manner to the subtracting circuit
43
, the subtracting circuit
47
calculates a differential value, pixel by pixel, between the output signal from the thin-out circuit
42
and the interpolated output signal from the interpolating circuit
49
. The differential signal provided by the subtracting circuit
47
is supplied to an encoding circuit
50
, which, in turn, supplies an encoded output signal to a second hierarchical output terminal
52
. In general, the interpolating circuits
46
and
49
are formed of interpolating filters. The encoding circuits
45
,
50
, and
48
perform compression-encoding upon the input signals supplied thereto.
Encoded differential signals corresponding to the first and second hierarchies are respectively provided at the output terminals
51
and
52
, and an encoded signal (not a differential signal) corresponding to the third hierarchy is provided at the output terminal
53
. It will be seen that in the conventional hierarchical encoding apparatus of
FIG. 8
higher-order hierarchical signals are obtained by thinning out lower-order hierarchical signals. With respect to each of the lower-order hierarchical signals, the apparatus forms differential data by subtracting an input signal from a higher-order interpolated signal. Then the highest-order signal, and the differential data in the other signals, are compression encoded.
A decoding apparatus which corresponds to the encoder of
FIG. 8
is illustrated in block diagram form in FIG.
9
. As shown in
FIG. 9
, the transmitted first, second and third hierarchical signals are respectively received by the decoding apparatus at input terminals
61
,
62
and
63
. A decoding circuit
64
is supplied with the third hierarchical signal received through the input terminal
63
, and a decoded output signal from the decoding circuit
64
is provided as a third hierarchical output signal at an output terminal
73
. The signal output from the decoding circuit
64
is also supplied to an interpolating circuit
67
.
The encoded differential signal corresponding to the second hierarchical level is supplied from the input terminal
62
to a decoding circuit
65
and the decoded differential signal output from the decoding circuit
65
is supplied to an adding circuit
68
. The adding circuit
68
adds the interpolated signal output from the interpolating circuit
67
and the differential signal received from the decoding circuit
65
to form a second hierarchical output signal which is provided at an output terminal
72
. The output signal from the adding circuit
68
is also provided as an input signal to an interpolation circuit
69
.
An encoded differential signal corresponding to the first hierarchical level is provided to a decoding circuit
66
from the input terminal
61
. The decoding circuit
66
outputs a decoded differential signal which is supplied to an adding circuit
70
. The adding circuit
70
adds an interpolated signal output from the interpolating circuit
69
and the decoded differential signal received from the decoding circuit
66
to form a first hierarchical output signal which is supplied to an output terminal
71
.
In the above-described conventional hierarchical encoding technique, as the number of hierarchical signal levels is increased, the amount of data to be transmitted also disadvantageously increases. For example, when two hierarchical signal levels are provided with thinning out at a rate of 1:4, the amount of data to be transmitted is increased by a factor of 1.25 (1+¼). With similar th

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