Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-05-07
2001-02-06
Utech, Benjamin (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S719000
Reexamination Certificate
active
06184145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which gate electrodes are formed through two etching processes.
2. Description of the Related Art
In conjunction with the fine pattern formation and high integration of a semiconductor integrated circuit, a wiring pattern size and a contact size are reduced in the semiconductor integrated circuit such as a DRAM. Also, the margin between the contact and the wiring pattern is reduced. As a result, a short-circuit becomes easly formed between the contact and a word line. Thus, it has become difficult to form a memory cell. To solve this problem, a method is known in which a pad polysilicon is used in the memory cell.
FIGS. 1A
to
1
G are cross sectional views of a conventional semiconductor memory device formed by a conventional manufacturing method.
As shown in
FIG. 1A
, element separation films
52
are selectively formed in the surface of a semiconductor substrate
51
to segment an element formation region. Subsequently, an oxide layer
53
is formed for a gate oxide film on the semiconductor substrate. Subsequently, a polysilicon layer
54
is formed for a gate lower electrode on the gate oxide film
53
to have the film thickness of 100 nm. Then, a WSi layer
55
is formed for a gate upper electrode on the polysilicon layer
54
to have the film thickness of 150 nm. Thus, the gate lower electrode and the gate upper electrode are formed for a word line and the gate electrode. After that, a mask oxide layer
56
is formed on the WSi layer
55
to have the film thickness of about 200 nm.
Next, as shown in
FIG. 1B
, a resist film
57
for the gate electrode is formed on the mask oxide layer
56
. Using the resist film
57
as a mask, the mask oxide layer
56
, the WSi layer
55
, and the polysilicon layer
54
are etched or patterned in order to form gate electrode structures. Then, N-type diffusion layers
58
are formed in the silicon substrate through opening portions between the gate electrode structures by an ion implantation process.
Next, as shown in
FIG. 1C
, an oxide layer is deposited on the whole surface of the silicon substrate
51
. The oxide layer is etched backed and removed to form side wall oxide films
59
for each of the gate electrode structure such that only a portion of the diffusion layers where a pad polysilicon region is to be formed is opened.
FIG. 2
shows a mask pattern which is used in this case. Also,
FIG. 3
is a plan view of a wiring layout pattern in the conventional semiconductor memory device. The element separation insulating films, the gate electrode structures and pad polysilicon patterns are shown in FIG.
3
. The oxide layer is etched back using the resist mask shown in FIG.
2
. In this way, the oxide layer in a peripheral circuit section and the oxide layer on the diffusion layer where pad polysilicon films are formed can be removed.
Next, as shown in
FIG. 1E
, a polysilicon layer
60
is deposited on the whole surface of the substrate
51
. Then, as shown in
FIG. 1F
, a resist pattern
61
for the polysilicon layer
60
is formed and the polysilicon layer
60
is etched for the pad polysilicon films. Subsequently, as shown in
FIG. 1G
, the resist pattern
61
is removed so that pad polysilicon films remain.
However, when the pad polysilicon films are formed by the above-mentioned conventional method, there is a part where the gate interval between the gate electrodes is wide. For this reason, a steep step
63
exists in the polysilicon layer. When there is the steep step, a part of the polysilicon layer is left near the side wall at the time of the etching process of the polysilicon layer
60
for the formation of the pad polysilicon films. The left part
62
functions a mask in the subsequent processes.
Also, in a photolithography process for the pad polysilicon films, the silicon substrate is possibly damaged at the time of the etching process of the polysilicon film because of variance of photoresist patterns in size and displacement between the diffusion layers and a mask for the pad polysilicon films. As an effective method for preventing the damage
64
of the substrate
51
, there is known a method of etching the polysilicon layer using as a mask, side wall oxide films larger than the photoresist pattern in size. However, in this method, the oxide film is left at the steep step section of the polysilicon layer. Thus, there is the problem that a portion of the polysilicon layer is not etched and is left.
In conjunction with the above conventional technique, a method of forming a contact in a semiconductor integrated circuit is disclosed in Japanese Examined Patent Application (JP-B-Heisei 7-105442). In this reference, a contact pad is formed in a contact hole between word lines. An oxide film of SOG, BPSG, TEOS, and PECVD oxide is formed on an element separation oxide film to minimize a step.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a semiconductor device such as a memory device with a thin and uniform pad polysilicon films.
Another object of the present invention is to provide a method of manufacturing a semiconductor device with simple and stable process.
In order to achieve an aspect of the present invention, a method of manufacturing a semiconductor device, includes:
forming a laminate film on an insulating film which is formed on a semiconductor substrate, the laminate film including a conductive layer and an insulating layer formed on the conductive layer;
performing a first etching process to the laminate film using a first mask to form a first group of patterns for first gates and a second group of patterns;
depositing a polysilicon layer for pad polysilicon films after the first etching process; and
performing a second etching process to the patterns of the second group using a second mask to form a third group of patterns for second gates.
The polysilicon layer is preferably deposited such that the polysilicon layer substantially fills a space between adjacent two of the patterns of the first and second groups.
The method may further includes forming side wall insulating films on side walls of each of the patterns of the first and second groups before the depositing.
Also, the method may further includes patterning the polysilicon layer to form the pad polysilicon films. In this case, a mask insulating film may be deposited on the polysilicon layer, the mask insulating film may be patterned, and then the polysilicon layer may be patterned using the patterned mask insulating film as a mask to form the pad polysilicon films. Instead, a mask insulating film may be deposited on the polysilicon layer, the mask insulating film may be patterned, side wall insulating films may be formed on side walls of the patterned mask insulating film, and then the polysilicon layer may be patterned using the patterned mask insulating film with the side wall insulating films as a mask to form the pad polysilicon films.
The semiconductor device may be a semiconductor memory device composed of a memory cell section and a peripheral circuit section, and the first gates are of transistors for the memory cell section, and the second gates are of transistors for the peripheral circuit section.
In order to achieve another aspect of the present invention, a method of manufacturing a semiconductor device, includes:
forming a laminate film on an insulating film which is formed on a semiconductor substrate, the laminate film including a conductive layer and an insulating layer formed on the conductive layer;
performing a first etching process to the laminate film using a first mask to form a first group of patterns for first gates and a second group of patterns;
depositing a polysilicon layer for pad polysilicon films after the first etching process;
forming an oxide mask on the polysilicon layer; and
patterning the polysilicon layer using the oxide mask as a mask; and
perfor
Deo Duy-Vu
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Utech Benjamin
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