Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1998-12-03
2001-02-06
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S060000, C257S061000, C257S062000, C257S063000, C257S064000, C257S065000, C257S055000, C257S056000, C257S057000, C257S058000, C257S347000, C257S348000, C257S349000, C257S355000
Reexamination Certificate
active
06184541
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to thin film transistors (hereinafter called TFT) employed in liquid crystal display devices (hereinafter called LCD) and manufacturing method of the TFT.
BACKGROUND OF THE INVENTION
As a main stream of thin and light-weighted displays, LCD are widely used in various displaying devices such as for notebook type personal computers, portable TVs, car-mounted navigators. The LCD device is also employed in compact high resolution displays such as viewfinders of video cameras. This compact high-resolution display is utilized in video projectors that have been demanded in the market in these days.
The TFT employed in a conventional type LCD is described with reference to FIG.
4
(
a
), a cross sectional view of the TFT, and FIG.
4
(
b
), an enlarged top view thereof.
This TFT comprises the following elements:
(a) an insulating substrate
1
(or, an insulating film formed on a semiconductor substrate);
(b) polycrystal semiconductor film
3
having grain boundary
2
, the film
3
is formed on the substrate
1
;
(c) source
6
and drain
7
each having an LDD structure that comprises a low concentration region
4
where impurity concentration is low, and a high concentration region
5
where impurity concentration is high, the source
6
and drain
7
are formed in the film
3
;
(d) a channel region
8
formed between the source
6
and drain
7
;
(e) a gate insulating layer
9
and a gate electrode
10
formed in this order on the channel region
8
;
(f) an inter-layer insulating film
11
having a contact hole and formed over the gate electrode
10
.
(g) an electrode wiring layer
12
made of conductive film and formed in the contact hole; and
(h) a passivation film
13
formed on the layer
12
.
In the conventional high resolution LCD device, an accurate ON-OFF characteristic of TFT switching performance is one of critical features. The accurate ON-OFF performance tells distinctly whether a voltage is supplied to a pixel electrode that applies a voltage to LCD or the voltage is not supplied, and controls a monochrome condition of every pixel, in other words, an entire display screen. In order to effect this accurate ON-OFF performance, it has been desirable that polycrystal silicon having a grain size as large as possible, e.g. 3-5 &mgr;m, is used for the polycrystal semiconductor thin film, thereby to increase an ON-current of the TFT.
The market recently demands to improve the picture quality; however, the LCD device having a conventional TFT structure encounters a problem that a large number of micro brighter spots occur when the display shows gray tone. The micro brighter spot illuminates brighter than a desired brightness, namely the micro brighter spot looks whiter than other pixels.
This problem is conditioned by two reasons. One is that TFT has been progressively miniaturized in order to gain luminance of a display screen through increasing an aperture rate of an LCD device. Another one is that an LCD device is subjected to a high temperature because the LCD is mounted to a video projector that employs brighter lamps.
A relation between the occurrence of micro brighter spot and a structure of the conventional TFT is described with reference to FIG.
4
(
b
). In the conventional TFT shown in FIG.
4
(
b
) employs silicon-made polycrystal semiconductor thin film of which grain size is 3-5 &mgr;m as an active layer of the TFT. The progress of TFT miniaturization entails such a phenomenon as the length “D” of each low concentration region
4
of the source
6
and drain
7
becomes shorter than the grain size. In manufacturing the TFTs, impurity ion is implanted so that the low concentration region
4
and high concentration region
5
are formed. When a heat treatment is provided for activation, highly concentrated impurity
14
implanted into the high concentration region
5
diffuses into the low concentration region
4
substantially along the grain boundary
2
. At this time, since the grain size is longer than the length “D” of the low concentration region
4
, the high concentration impurity
14
diffuses deeply along the grain boundary
2
, thereby to shorten an effective length “d” of the low concentration region
4
. As a result, an OFF effect of the TFT switching characteristic is lowered. Even the TFT is in an OFF state, when the LCD is subjected to a high temperature, a leakage current enough to produce micro brighter spots runs between the source and the drain of TFT. The micro brighter spots are thus produced.
SUMMARY OF THE INVENTION
The present invention aims to provide a small size TFT that can prevent micro brighter spots from occurring when an LCD is used in a high temperature atmosphere.
The TFT of the present invention comprises the following elements:
(a) an insulating substrate, or a semiconductor substrate on which an insulating film is formed;
(b) polycrystal semiconductor thin film formed on the insulating substrate or the insulating film, and having a source and a drain in an LDD structure that has a low concentration region where impurity concentration is low as well as a high concentration region where impurity concentration is high;
(c) a gate insulating film formed on the plycrystal semiconductor thin film; and
(d) a gate electrode formed on the gate insulating film.
The length of low concentration region measured from the edge of gate insulating film is not smaller than an average grain size of the polycrystal semiconductor thin film.
A manufacturing method of the TFT of the present invention comprises the following steps:
(i) forming an amorphous semiconductor film on one of an insulating substrate and an insulating film formed on a semiconductor substrate;
(ii) forming a polycrystal semiconductor film by providing a heat treatment to the amorphous semiconductor film;
(iii) forming a gate insulating film and a gate electrode sequentially on the polycrystal semiconductor film;
(iv) forming a source and a drain both having low impurity concentration by implanting impurity ion into the polycrystal semiconductor film across an area from the edge of gate insulating film to at least a distance of an average grain size,
(v) forming the source and the drain both having high impurity concentration by implanting the same conductive type impurity ion as used in the low concentration region into the region other than the low concentration region; and
(vi) providing a heat treatment for activating the source and drain where ion has been implanted.
The above structure and method provide polycrystal semiconductor film having a small average grain size. Therefore, even if the impurity diffuses from the high concentration region into the low concentration region along the grain boundary at the heat treatment that activates the impurity, a grain boundary parallel to the gate electrode restrains the diffusion. An effective length “d” of the low concentration region is thus restrained from being shorter. Therefore, a TFT composing each pixel can be smaller in size, and the micro brighter spots in gray-tone-display can be prevented from occurring in a high temperature atmosphere because a leakage current of the TFT is restrained.
REFERENCES:
patent: 5-308081 (1993-11-01), None
patent: 09008314 (1997-01-01), None
Kobayashi et al., “A Novel Fabrication Method for Poly-si TFTs with a Self-Aligned LDD Structure”, Int'Conference on Solid State Devices and Materials, Aug. 1, 1992, p. 693-694.
Seki et al., “Laser-recrystallized polycrystalline-silicon thin-film transistors with low leakage current and high switching ratio”, IEEE Electron Device Letters, Sep. 1987, vol. EDL-8, No. 9, pp. 425-427.
Kim et al., “Degradation Due To Electrical Stress of Poly-Si Thin Film Transistors With Various LDD Lengths”, IEEE Electron Device Letters, vol. 16, No. 6, Jun. 1, 1995, pp. 245-247.
Int'l Search Report for Int'l Appln. No. Ep 98 12 2700 dated Sep. 16, 1999.
Ito Yutaka
Oka Hitoshi
Abraham Fetsum
Matsushita Electronics Corporation
Ratner & Prestia
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