Method for monitoring self-aligned contact etching

Details Method for monitoring self-aligned contact etching Method for monitoring self-aligned contact etching

1997-08-26

2001-02-06

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S743000

Reexamination Certificate

active

06184149

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating integrated circuits, and more particularly, to a method for monitoring self-aligned contact etching.
2. Description of the Prior Art With the development of the semiconductor process, the width of the metal line can be manufactured in a very narrow range. In an integrated circuit process, a contact hole provides an electrical connect for interconnections with the active region of a semiconductor device. Typically, the contact hole is formed using an etching process. The contact hole is typically generated by etching an insulator layer employing a photoresist as an etching mask. The contact hole provides a portion of active area of semiconductor device for interconnections between semiconductor devices. Referring to
FIG. 1
, semiconductor devices
4
such as transistor are formed over a semiconductor substrate
2
. Sidewall spacers
6
and liner layer
8
are substantially formed on the substrate
2
by using a conventional deposition and etching process. An insulator layer
10
such as oxide is then deposited on the liner layer
8
. A photoresist layer
12
is coated on the insulator layer
10
and patterned as an etching mask. Afterward, a self-aligned contact (SAC) etching process is performed with high etching selectivity of spacer or liner (for example S
i
N) to insulator layer (for example oxide). The self-aligned contact (SAC) etching process can shrink the contact design rule.
During SAC etching, the reaction gas of carbon-fluorine-contained compounds under plasma generates polymer which can etch oxide layer with high etching selectivity of S
i
N film to oxide layer. However, too much polymer deposition may cause oxide layer
10
etching stop while insufficient polymer may result in undesirable etching loss of S
i
N spacer or liner layer. Therefore, a method to monitor the SAC etching chamber is important for mass production especially under such high polymer deposition condition. Generally, a wafer with SAC structure is etched and inspected by cross-section SEM for checking S
i
N loss and etching stop. However, wafers with SAC structure take a long preparation time and high cost in preparation. Generally, it spends time about three weeks to one month to finish complex steps from forming gate electrode to oxide layer. In addition, a few hundred angstrom SN loss is not easy to characterize. Therefore, a method is needed for accurately monitoring the chamber condition and the corresponding SN selectivity with low running cost.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a method for monitoring an etching process. The conventional method for monitoring self-aligned contact etching takes long wafer preparation time and involves a high cost in wafer preparation. The present inventions propose a novel method to monitor SAC etching at a low cost and with a rapid wafer preparation.
A semiconductor wafer is used as a control wafer in the present invention. A thick oxide layer is then formed on the substrate. The oxide control wafer is etched using a recipe that is the same as the SAC recipe. A photoresist pattern is formed on the oxide layer with a window of a contact hole. The width of the window is the same as that of the SAC etching process. After etching oxide control wafer, the contact hole is formed. Applying the SEM micrograph to inspect the cross-section profile of the contact hole, the depth of etching profile transition depth and the depth of etching stop can be observed in the oxide control wafer. The profile transition occurs when the polymer deposition rate is faster than the etching rate of the polymer. The depth of etching profile transition for the oxide control wafer corresponds to the etched thickness of the S
i
N corner loss for the SAC wafer. This depth of profile transition in the oxide control wafer can be used to monitor SAC etching chamber condition. Additionally, the depth of etching stop in the oxide control wafer can be employed for detecting the shift of chamber condition in early stage.


REFERENCES:
patent: 3664942 (1972-05-01), Havas et al.
patent: 5631184 (1997-05-01), Ikemasu et al.
patent: 5694207 (1997-12-01), Hung et al.
patent: 5783496 (1998-07-01), Flanner et al.
A.J. VanRoosmalen et al., “Dry Etching for VLSI”, Plenum Press, N.Y, 1991, p. 109.

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