Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-03-09
2001-02-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S230030
Reexamination Certificate
active
06195280
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to memory arrays in data processing systems.
BACKGROUND INFORMATION
Standard memory circuits, according to the prior art, use a common bus to read, write and refresh the bitlines. In
FIG. 1. a
memory
100
according to the prior art is illustrated. Memory
100
includes two columns of memory cells, bitline column
101
and bitline column
102
. Each bitline includes a plurality of memory cells for the storage of data. For ease of illustration, bitline column
101
and bitline column
102
are each shown to include four memory cells, memory cells
103
-
106
in bitline column
101
, and memory cells
107
-
110
in bitline column
102
.
Prior to any read or write operation, the bitlines are precharged to V
DD
. Precharge is initiated by asserting bitline precharge signal
111
thereby turning on p-type metal oxide semiconductor (PMOS) devices
112
-
114
in precharge circuit
115
, and PMOS devices
116
-
118
in precharge circuit
119
, respectively. PMOS device
114
equalizes bitlines
120
and
121
which are then pulled to V
DD
through PMOS devices
112
and
113
. Similarly, bitlines
122
and
123
are equalized by PMOS device
118
and pulled to V
DD
by PMOS devices
116
and
117
, respectively.
The precharge rate is limited by the capacitance on the bitlines. This limits the cycle time for memory
100
. The capacitance on the bitline arises from the bitline wire capacitance and the capacitance of the semiconductor devices within the memory cells
103
-
106
, and
107
-
110
. As the number of cells on a bitline increases, the capacitance increases proportionately. Thus, as the size of memory
100
increases, the cycle time also increases as well.
After the bitlines are precharged, bitline precharge signal
111
is negated, turning off PMOS devices
112
-
114
, and
116
-
118
. Data can then be read from, or written to, one of memory cells
103
-
110
. For a write operation, a data value on Data In line
124
, and its complement on {overscore (Data In)} line
125
are transferred to bitlines
120
or
122
and
121
or
123
, respectively, via n-type metal oxide semiconductor (NMOS) devices
126
,
127
,
128
and
129
. Data is transferred in response to a write select signal asserted on write select
130
if the write is to be made to one of memory cells
103
-
106
in bitline column
101
, or on write select
131
if a write is to be made to one of memory cells
107
-
110
in bitline column
102
. Asserting the write select signal on write select
130
turns on NMOS devices
126
and
127
, and asserting a write select on write select
131
turns on NMOS devices
128
and
129
. The turning on of NMOS device
126
couples Data In
124
to bitline
120
, and the complementary data value on {overscore (Data In)}
125
to bitline
121
. Similarly, asserting write select
131
, thereby turning on NMOS devices
128
and
129
, couples Data In
124
to bitline
122
in bitline column
102
, and the complementary data value on {overscore (Data In)}
125
to bitline
123
in bitline column
102
. Depending on the data value, one of Data In
124
, and {overscore (Data In)}
125
is logic “1” and the complementary input is logic “0.” The coupling of bitlines
120
and
121
to Data In
124
and {overscore (Data In)}
125
, respectively, if write select
130
is asserted, or bitlines
122
and
123
to Data In
124
and {overscore (Data In)}
125
, respectively, if write select
131
is asserted, discharges the precharge on the bitlines. The one of bitlines
122
and
123
that is coupled to the one of Data In
124
or {overscore (Data In)}
125
that is logic “0” is discharged to ground. Thus, the write operation also requires discharging of the capacitances appearing on the bitlines, and therefore, the write time performance of the memory is also limited by the bitline capacitance.
Hence, there is a need in the art in which the bitline capacitances that the precharge circuitry is required to charge during the precharge operation, or the write circuitry is required to discharge during a write operation, are reduced. The reduction of this capacitance improves the performance of such memory by reducing the precharge time, and the time required to write to such memory, permitting faster memory cycle rates.
SUMMARY OF THE INVENTION
The previously mentioned needs are addressed by the present invention. Accordingly, there is provided in a first form, a memory system having a unidirectional write bus. The memory includes a plurality of memory cell groups, each including a plurality of memory cells, and a plurality of first bitlines coupled to a corresponding one of the plurality of memory cell groups. Each of the first bitlines communicates write data for writing to one of the memory cells in the corresponding memory cell group. The memory further includes at least one second bitline coupled to each of the first bitlines, the second bitline communicating read data for reading from one of the memory cells. The second bitline is decoupled from each of the first bitlines during a write to one of the memory cells.
There is provided, in a second form, a method of communicating with a memory system. For a write operation, a plurality of first bitlines is decoupled from a second bitline and coupled to a data line. One bitline and associated memory cell group is selected for writing, and coupled to a data line for transmitting data to the associated memory cell group.
Additionally there is provided, in a third form a data processing system including a processor coupled via a bus to a storage system, a memory system, and an input/output system, wherein a memory system is located within one of said processor, storage system, memory system, or input/output system. The memory system contains a plurality of memory cells wherein the plurality of memory cells is partitioned into first and second memory cell groups. A first bitline is coupled to the first memory group and a second bitline is coupled to the second memory group. A third bitline is coupled to the first and second bitlines for communicating read data from the first and second memory cell groups, and a data line is coupled to said first and second bitlines for communicating write data to the first and second memory cell groups.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5892725 (1999-04-01), Lattimore et al.
patent: 6058065 (2000-05-01), Lattimore et al.
Lattimore George McNeil
Lotfi Younes
Ross, Jr. Robert Anthony
Yeung Gus Wai-Yan
England Anthony V. S.
International Business Machines - Corporation
Nelms David
Tran M.
Winstead Sechrest & Minick P.C.
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