Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-08-30
2001-12-11
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S691000, C257S736000, C257S750000, C257S758000, C257S767000, C257S775000, C257S781000, C257S784000, C257S786000, C361S748000, C174S261000
Reexamination Certificate
active
06329719
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to improvement of the reliability of wire structures for connecting wires or conductors, which are formed on different layers, by using via holes.
2. Description of Related Art
In general, a metal wire in a semiconductor device is formed by patterning a metal thin film by a photolithography or etching technique. According to the type of each circuit, the thickness of the metal thin film ranges from about 300 nm to about 1000 nm, and the material used therefor is an aluminum alloy, titanium (Ti), titanium nitride (TiN) or other metal having a high melting point. The linewidth is determined by the amount of current flowing through the wire. The amount of current per unit sectional area of wire has been decided for each type of wire material to prevent problems attributable to electromigration, the established amount of current being known as permissible current density. For instance, when more current need to flow through a wire, a wider wire is used. Normally, a wider wire exhibits higher resistance to electromigration than a narrower wire; hence, a wire of a predetermined width or more is capable of retaining reliability even when the amount of current per unit sectional area is increased. For this reason, there is a trend toward increasing the permissible current density of a wide wire.
The recent trend toward multi-layer wiring requires that the reliability of wires be guaranteed in two or more layers electrically connected through via holes. This has led to a difficulty in increasing the permissible current density of the conventionally used wide wires, or it has even made it inevitable to decrease the permissible current density because a larger linewidth means a shorter electromigration life. This has resulted in an inconvenience in that the linewidth has been further increased, interfering with an attempt to make devices with even finer patterns or higher integration.
There has been another inconvenience in that, when electrical connection is made through a via hole between an upper layer wire and a lower layer wire orthogonally formed, concentration of current occurs around the via hole formed on the side of an interior angle of the orthogonal area, and voids due to electromigration tend to be produced in the neighborhood.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device with high reliability that has an extended electromigration life of the wires electrically connected with conductors of different layers through via holes.
To this end, according to one aspect of the present invention, there is provided a semiconductor device comprised of: a first wire that has a plurality of via holes formed in the vicinity of an end thereof and that is connected with a conductor of a different layer through the via holes; and a plurality of slits that are provided parallel to a direction in which the first wire extends and that split the first wire into a plurality of second wires over only a predetermined distance from the end.
According to another aspect of the present invention, there is provided a semiconductor device comprised of: a first wire; a second wire of a layer different from that of the first wire, the second wire extending in a direction at right angles to the first wire; a connection area where a portion in the vicinity of an end of the first wire intersects with a portion in the vicinity of an end of the second wire; a plurality of first slits that are provided parallel to the direction in which the first wire extends and that divide the first wire into a plurality of third wires over only a predetermined distance from the end thereof; a plurality of second slits that are provided parallel to the direction in which the second wire extends and that divide the second wire into a plurality of fourth wires over only a predetermined distance from the end thereof; and a plurality of via holes that are formed in the connection area and that connect the plurality of third wires and the plurality of fourth wires.
REFERENCES:
patent: 3270399 (1966-09-01), Ohntrup
patent: 5329162 (1994-07-01), Nadaoka
patent: 5498909 (1996-03-01), Hasunuma et al.
patent: 5506450 (1996-04-01), Lee et al.
patent: 5723908 (1998-03-01), Fuchida et al.
patent: 5955788 (1999-09-01), Iwasa
Jones Volentine PLLC
Lee Eddie
OKI Electric Industry Co., Ltd.
Warren Matthew E.
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