Self-modifying code handling system

Details Self-modifying code handling system Self-modifying code handling system

1996-01-26

1998-10-20

Harrell, Robert B.

G06F 900

Patent

active

058260730

ABSTRACT:
A processor which includes tags indicating memory addresses for instructions advancing through pipeline stages of the processor and which includes an instruction decoder having a store target address buffer allows a self-modifying code handling system to detect store operations writing into the instruction stream and trigger a self-modifying code fault. In one embodiment of a seIf-modifying code handling system, a store pipe is coupled to a data cache to commit results of a store operation to a memory subsystem. The store pipe supplies a store operation target address indication on commitment of a store operation result. A scheduler includes ordered Op entries for Ops decoded from instructions and includes corresponding first address tags covering memory addresses for the instructions. First comparison logic is coupled to the store pipe and to the first address tags to trigger self-modifying code fault handling means in response to a match between the store operation target address and one of the first address tags. An instruction decoder is coupled between the instruction cache and the scheduler. The instruction decoder includes instruction buffer entries and second address tags associated with the instruction buffer entries. Second comparison logic is coupled to the store pipe and to the second address tags to trigger the self-modifying code fault handling means in response to a match between the store operation target address and one of the second address tags.

REFERENCES:
patent: 5226130 (1993-07-01), Favor et al.
patent: 5434987 (1995-07-01), Abramson et al.
patent: 5692167 (1997-11-01), Grochowski et al.
Anderson, et al.: "Instruction prefetching interlock", Jul. 1967, pp. 125-126, IBM Technical Disclosure Bulletin, XP000615113.

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