Semiconductor device with partial passivation layer

Details Semiconductor device with partial passivation layer Semiconductor device with partial passivation layer

2000-01-21

2001-11-06

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S762000

Reexamination Certificate

active

06313538

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing, and, more particularly, to a method for forming a semiconductor device with partial passivation layers.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. Many modem integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductive substrate.
The conductive interconnect structures are typically accomplished through the formation of a plurality of conductive lines and conductive plugs, commonly referred to as contacts or vias, formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another.
A contact is generally used to define an interconnect structure (e.g., using polysilicon or metal) to an underlying polysilicon layer (e.g., source/drain or gate region of a transistor), while a via denotes a metal to metal interconnect structure. In either case, a contact opening is formed in a dielectric layer overlaying the conductive member. A second conductive layer is then formed in the contact opening and electrical communication is established with the contact member.
Commonly, passivation layers, such as silicon nitride, are formed between device layers of the semiconductor device. In cases where copper is used to form the conductive lines and interconnects in the semiconductor device, the passivation layer acts as a barrier layer to prevent diffusion of the copper and as an antireflective coating for subsequent photolithography. After forming the passivation layer, an inter-level dielectric (ILD) layer is formed. The ILD layer isolates the overlaying layers and provides the dielectric base in which subsequent lines and interconnects of the next device layer are formed. Commonly used ILD materials are tetraethoxysilane (TEOS) and fluorine doped TEOS (F-TEOS). A new class of dielectric materials, commonly referred to as low-k dielectrics, have also been employed for ILD layers. Low k dielectrics typically have a dielectric constant less than 3.0 and thus provide enhanced isolation functions to allow reduced device sizes. A commonly available low k dielectric material is Black Diamond, sold by Applied Materials, Inc.
One disadvantage of passivation layers is that their dielectric constants are typically higher than those of the ILD layers. This increases the line-to-line capacitance of the particular layer being covered. Hence, the effective dielectric constant of the layer is increased, potentially reducing the performance of the device.
Another disadvantage of passivation layers is that they are optically more dense than the ILD layers. As subsequent layers are formed on the semiconductor device, they are aligned with the first metal layer or the substrate by evaluating the strength of an electrical signal imposed thereon. The increased density of the passivation layers reduces the accuracy of the alignment process, giving rise to a higher number of potential alignment errors as the number of layers increases.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a semiconductor device including a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer.
Another aspect of the present invention is seen in a method for forming a semiconductor device. The method includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.


REFERENCES:
patent: 5751066 (1998-05-01), Havemann
patent: 5970373 (1999-10-01), Allen
patent: 6040628 (2000-03-01), Chiang et al.
patent: 6188135 (2001-02-01), Chan et al.

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