Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
1999-01-06
2001-12-25
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C324S512000
Reexamination Certificate
active
06334097
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of determining the lethality of defects in the circuit pattern inspection, a method of selecting defects to be treated as review objects, and the circuit pattern inspection system involved with these methods. Particularly, the invention relates to a method of efficiently determining, in a manufacturing process to form semiconductor devices on a semiconductor wafer, whether a defect detected by an appearance/particle inspection instrument is lethal in accordance with the characteristics of circuit patterns of the semiconductor devices, a method of efficiently selecting a defect that should be treated as a review object when defects are detected, in accordance with the characteristics of defects generated on each process, and the system involved with the above methods.
2. Description of the Related Art
In the semiconductor manufacturing process, it is essential for maintaining or enhancing the yield to detect the cause of a failure as quickly as possible and feedback the countermeasure to the process and/or the manufacturing facilities. In order to establish the countermeasure, it is important to detect a failure by an inspection instrument and analyze the inspection data.
As the conventional technique in this field, defects such as pattern shorts and a pattern missing which are generated on the wafer process, and particles are automatically inspected by, for example, the inspection instruments using an image processing and dark field irradiation by laser beams.
These inspection instruments output the coordinate data of defects and particles in the semiconductor wafer, and the sizes of the defects to an analysis system that stores these data. Next, the inspected wafer is moved onto a stage of an optical microscope or scanning electron microscope, the stage is moved to the position corresponding to the coordinate data of a detected defect, and the defect is classified by the magnified image thereof. This classification work is called the review.
This review has two objects.
One is to classify defects detected in accordance with the characteristics of the defects themselves, such as pattern missing, pattern shorts, film residue, particles, etc.
Another one is to determine whether a defect leads to a lethal defect for the function of the semiconductor device, and from the result to classify the defect into a lethal defect or non-lethal defect.
After completing the review, a review station outputs the classification identifiers predetermined in accordance with the classification and lethality
on-lethality of the defects themselves to the analysis system that analyzes the data.
The foregoing conventional technique has become an essential technique for enhancing the yield when forming circuit patterns on a semiconductor wafer through the micro fabrication.
On the process of manufacturing a semiconductor wafer, if a defect is detected, occasionally the defect cannot be any obstacle to the operation. If there are particles on the wafer, to regard all the semiconductor chips made therefrom as failure is to treat even the normally operating chips as failure. That is impractical.
Therefore, the determination as to whether the defect is lethal or not is specially important in the inspection process. However, the conventional technique involves the following problems in the determination of the defect being lethal or not.
In the conventional technique, the review and the determination of lethality are carried out by human hands and brains, and therefore, the work needs a considerable time, which will become a hindrance to enhancing the throughput of the total inspection process.
In regard to the determination of lethality, the inspector needs to have the knowledge of functions and structures of the circuit patterns of a defective area as well as the discrimination of the defects themselves, and the work is entrusted to specialists having those specific knowledge. Further, the determination criterion of lethality differs among these specialists, and the result of determination varies depending on the inspector, which is a problem.
If the determination of lethality by the review is not conducted at all on the pretext of the throughput, or the determination of only a part of defects is conducted, the following inconveniences will arise.
This problem will be described with reference to FIG.
19
.
FIG. 19
illustrates a graph in which a relation between the total number of defects and the yield is plotted, and a graph in which the total number of defects produced in time series on each of inspection wafers is plotted.
As shown in FIG.
19
(
a
), there is not a correlation between the total number of defects and the yield of the semiconductor chips, and thereby a significant control limit cannot be introduced. Here, the control limit signifies the number of defects that is provided for controlling the quality. The yield indicates the rate of non-defectives against all the chips on a wafer.
Accordingly, as shown in FIG.
19
(
b
), although the total defect number by each inspection wafer is plotted in time series to thereby predict the abnormality of the yield and to thereby take a countermeasure in an earlier stage, since the total defect number does not function as a monitor value, the setting of a control limit will not bring about a good detection of abnormality. In the example of this drawing, since the total defect number exceeds the control limit in every point, all the defects are to be determined as abnormal.
During the review, it is necessary to view an enlarged image by the optical microscope or scanning electron microscope, which accompanies the works of moving the stage, bringing the defect into the field of view, focusing and the like. Therefore, to carry out the reviews of all the defects detected by the inspection instrument will be a contradiction against the requirement for enhancing the throughput in the inspection process. Accordingly, it is necessary to reduce the number of the defects of the review object, however, this work to reduce the number is entrusted to the review operator; and the selection results of the review object will differ depending on the operators, which is a problem.
The present invention has been made to resolve the foregoing problems, and it is therefore an object of the invention to provide a method of determining the lethality of defects, which enhances the efficiency of inspection by automatically determining the lethality of defects without conducting the review when inspecting circuit patterns formed on a substrate of a semiconductor wafer or the like, and an inspection system to implement the same.
Another object of the invention is to provide a method of automatically selecting defects to be reviewed in order to efficiently perform the review in the inspection of the circuit patterns while maintaining the quality of the inspection itself, and an inspection system to implement the same.
SUMMARY OF THE INVENTION
In order to accomplish the foregoing objects, the invention sets forth a construction relating to a method of determining a lethality of defects in an inspection of circuit patterns formed on a substrate, as follows. At an inspection stage, inspection data of the defects produced on the circuit patterns are generated, the inspection data generated are inputted to be processed; and thereby, the lethality of the defects corresponding to the inspection data are determined.
In detail, the foregoing method of determining the lethality employs the coordinate data of the circuit patterns and the sizes of the defects as the inspection data.
Further in detail, the foregoing method of determining the lethality of defects segments each of the circuit patterns into several areas having different characteristics, and serves the data to determine the lethality of the defects as determination rules each provided for each of the areas of the circuit patterns.
To achieve the foregoing objects, the invention sets forth a further detailed construction relating to
Shiba Masataka
Shimoda Atsushi
Yoshitake Yasuhiro
Hitachi , Ltd.
Hoff Marc S.
Raymond Edward
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