Integrated circuit device having a core controller, a bus...

Details Integrated circuit device having a core controller, a bus... Integrated circuit device having a core controller, a bus...

1998-11-25

2001-11-27

Tung, Kee M. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

C345S520000, C345S535000, C345S542000, C710S120000, C710S120000

Reexamination Certificate

active

06323866

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an integrated circuit device for use in a computer system, more particularly to an integrated circuit device that has a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein.
2. Description of the Related Art
Referring to
FIG. 1
, a conventional personal computer system
1
is shown to comprise a central processing unit (CPU)
10
, a host bus
11
connected to the CPU
10
, a core logic
12
connected to the host bus
11
, a memory bus
13
connected to the core logic
12
, a system memory
14
connected to the memory bus
13
, an input/output (I/O) bus
15
connected to the core logic
12
, at least one peripheral device
16
connected to the I/O bus
15
, an Advanced Graphical Port (AGP) bus
17
connected to the core logic
12
, a stand-alone video graphic accelerator (VGA) card
18
connected to the AGP bus
17
, and a monitor
19
connected to the VGA card
18
. The VGA card
18
includes a VGA chip
181
, a local frame buffer
182
formed from dynamic memory, and a flash memory
183
for VGA BIOS.
Referring to
FIG. 2
, it has been proposed heretofore in another conventional personal computer system
2
to discard the stand-alone VGA card, and mount the VGA chip
281
and the local frame buffer
282
directly on the system board (not shown) to reduce costs and simplify manufacture of the system board.
Referring to
FIG. 3
, it has also been proposed heretofore in still another conventional personal computer system
3
to employ a unified memory architecture (UMA) in order to result in more cost savings by reducing the system board space and the components on the system board (not shown). As shown, the personal computer system
3
comprises a CPU
30
, a host bus
31
connected to the CPU
30
, a core logic
32
connected to the host bus
31
, an I/O bus
35
connected to the core logic
32
, at least one peripheral device
36
connected to the I/O bus
35
, an AGP bus
37
connected to the core logic
32
, a VGA chip
38
connected to the AGP bus
37
, a shared system memory
34
, and a wired-or memory bus
33
interconnecting the core logic
32
, the VGA chip
38
and the shared system memory
34
. Since the VGA chip
38
shares the system memory
34
with the core logic
32
, the need to provide a dedicated local frame buffer for the VGA chip
38
is therefore obviated.
However, in order to enable the VGA chip
38
and the core logic
32
to share the system memory
34
, some protocol must be introduced for the VGA chip
38
and the core logic
32
to follow. There is thus a need to incorporate additional pins and interface signals into the VGA chip
38
and the core logic
32
for protocol communication. Referring again to
FIG. 3
, the VGA chip
38
issues the MREQ# signal to inform the core logic
32
of its need to use the memory bus
33
for data transmission. After internal arbitration by the core logic
32
, the core logic
32
releases the memory bus control to the VGA chip
38
, and indicates the released state to the VGA chip
38
via the MGNT# signal. At this time, the memory access cycle of the VGA chip
38
can proceed as long as the MGNT# signal is driven to an active state by the core logic
32
. The memory access cycle of the VGA chip
38
is terminated when the MGNT# signal becomes inactive, except in cases where the VGA chip
38
issues a high priority signal (not shown) to the core logic
32
.
Furthermore, since there is a switching penalty whenever the memory bus control is switched from the core logic
32
to the VGA chip
38
, and vice versa, the wired-or architecture of the memory bus
33
will downgrade the system performance.
FIG. 4
shows detailed pin constructions of the memory control signals which are driven by the core logic
32
and the VGA chip
38
onto the memory bus
33
for data transmission.
FIG. 5
shows the switching overhead that is incurred whenever the memory bus
33
is switched between the core logic
32
and the VGA chip
38
. As illustrated, the time period T
1
between activation of the MREQ# signal and activation of the MGNT# signal depends on whether or not the memory bus is idle and on the internal arbitration algorithm of the core logic
32
. The length of the time period T
2
, i.e. the length of the MGNT# signal, depends on the VGA data transmission length and on the presence of a memory request from other master devices with a higher priority than the VGA chip
38
. In time period T
3
, if there is a memory request from another master device with a higher priority, the core logic
32
will cease to assert the MGNT# signal to inform the VGA chip
38
to stop its data transmission by deactivating the MREQ# signal. Otherwise, the core logic
32
will only cease to assert the MGNT# signal after the VGA chip
38
has finished its data transmission and has inactivated the MREQ# signal.
Because the memory bus
33
has the wired-or architecture, when one of the core logic
32
and the VGA chip
38
assumes control of the memory bus
33
, it becomes responsible for driving all control signals to the system memory
34
to ensure proper functioning of the latter. Whenever the control of the memory bus
33
is switched from one master to another, the original master of the memory bus
33
should drive all the control signals of the memory bus
33
to a high voltage level for at least one clock cycle, and subsequently float the memory bus
33
by deactivating the output (o/p) enable pins of the corresponding memory bus signals (see
FIG. 4
) to avoid bus contention. In this manner, at least four clock signals are wasted due to bus switching when the control of the memory bus
33
is switched from one master to another. Moreover, in order to meet timing requirements of the system memory
34
, such as RAS# pre-charge time, both the core logic
32
and the VGA chip
38
must finish the RAS# pre-charge time before they switch the memory bus
33
and after they get control of the memory bus
33
in order to avoid compatibility issues in the event that the core logic
32
and the VGA chip
38
are made by different chip vendors.
It is also noted that the conventional personal computer system
3
involves overhead in translating data from one bus protocol to another bus protocol, i.e. the generation of data in the form of the destination bus protocol. Synchronization penalty is further incurred if the clock domain of the source bus is different from that of the destination bus.
Translating the host data destined for the VGA chip
38
in the conventional personal computer system
3
normally comprises three phases: the initiate phase, the translated phase, and the response phase. The initiate phase starts from the cycle request from a current host bus owner to the generation of an intermediate request. The translated phase starts from the intermediate request to the completion of the cycle on the destination bus. The response phase starts from the completion of the cycle by a response agent on the destination bus to the completion of the cycle on the originating bus. In most cases, the initiate phase on the originating bus and the response phase on the destination bus perform at different clock domains. In the conventional personal computer system
3
of
FIG. 3
, the initiate phase is performed on the 100 MHZ X86-like host bus
31
, while the response phase is performed on the 66 MHz AGP bus
37
.
Therefore, in the event of an incoming transaction to the AGP bus
37
, synchronization must be performed before entering the translated phase owing to communication between the two different clock domains.
FIG. 6
illustrates a synchronizer
39
for performing the aforesaid synchronizing function. The synchronizer
39
is separated into an input stage
391
and an output stage
392
. The input signal at the input stage
391
is sampled using an input clock. The output signal of the input stage
391
serves as an input to the output stage
392
, and is sampled us

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