Oscillators – Ring oscillators
Reexamination Certificate
2000-03-08
2001-11-13
Kinkead, Arnold (Department: 2817)
Oscillators
Ring oscillators
C365S222000, C327S534000, C327S548000
Reexamination Certificate
active
06317007
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) devices. More particularly, the present invention relates to a delayed start oscillator of especial utility with respect to dynamic random access memory (“DRAM”) devices or other integrated circuit devices having a self-refresh or other modes of operation requiring an initial start-up delay in entering the particular mode.
Current IC memory devices may utilize an on-chip oscillator to generate a signal with a desired frequency to enable memory access operations. Among those which may be utilized are complementary metal oxide semiconductor (“CMOS”) ring oscillators. These oscillators utilize an odd number of inverting stages, each comprising a P-channel and N-channel transistor, to provide the correct polarity of feedback for the circuit. In general, the frequency of oscillation for a ring oscillator is determined by the collective inverter propagation delays. Presently, all such oscillators cycle at a constant rate and without the ability to provide a selectively delayed start-up time.
SUMMARY OF THE INVENTION
The delayed start oscillator of the present invention is operational to provide an output clock signal at a constant rate following a selectively delayed startup time and can be used, for example, in dynamic memory cell-based integrated circuit devices incorporating a self-refresh mode or other special modes of operation wherein an initial start-up delay in entering the particular mode is desired and in which the initial delay is longer than the clock period of the signal then controlling the mode.
Particularly disclosed herein is a delayed start oscillator comprising an oscillator enable signal having first and second states thereof for selectively enabling and disabling the oscillator respectively; an oscillator output signal having first and second levels thereof responsive to the first state of the oscillator enable signal for providing an oscillator output signal; a timing circuit coupled to a supply voltage line for providing a timing signal output indicative of a selected delayed start duration; and a plurality of series connected inverting stages coupled to receive the oscillator output signal and the timing signal. The oscillator output signal remains at a first level thereof for the delayed start duration in response to the timing signal and subsequently transitions between the first and second levels at an operational frequency determined by the plurality of inverting stages until the oscillator enable signal transitions to the second state thereof.
REFERENCES:
patent: 6163225 (2000-12-01), Sundaram et al.
Butler Douglas B.
Parris Michael C.
Hogan & Hartson LLP
Kinkead Arnold
Kubida William J.
Langley Stuart T.
United Memeories, Inc.
LandOfFree
Delayed start oscillator circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Delayed start oscillator circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delayed start oscillator circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2574640