Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-07-12
2001-10-02
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S720000, C438S722000
Reexamination Certificate
active
06297161
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating array bus by using taper etching, and more particularly, to a method for fabricating TFT (Thin-Film Transistor) array bus by using taper etching.
2. Description of the Prior Art
Unlike the case in the IC industry, there were so many metal materials been used in the development history of TFT process. However, the trend for larger size and higher resolution makes it inevitable to use the Aluminum as the major conducting material for the transmission bus of the TFT array due to its low resistivity. When using aluminum as the bus material, usually a multi-layer metal structure is used because of the poor contact property between Aluminum and other materials. For example, the Ti/Al/Ti structure was proposed for the source/drain bus in the top ITO TFT array process. In the previous structure, the Ti acts as the barrier layer. The bottom Ti serves as the barrier between Al and the underlying N+ layer to improve the ohmic contact property, whereas the top Ti is to improve the contact between Al and the ITO. In addition to the Ti/Al/Ti structure, other material combinations were also proposed for the Al based transmission bus. The common feature is that multi-layer structure with barrier layer must be used.
Although the poor contact property of Al can be solved by the application of the barrier layer, the multi-layer structure raise new process issues, especially in the etching process. Basically, metal etching can be performed by either dry etching or wet etching. For example, Ti/Al/Ti is usually etched by dry etching. The advantage of the dry etching is easier for profile control. The profile control is extremely important in the TFT process. Since the planarization technology is not mature in the TFT process yet, the taper profile of each layer is required to prevent the bad step coverage of the following layers. Although dry etching is a good method for profile control, the selectivity to the underlying Si layer raise another concern. Moreover, the equipment maintenance is a hard job. The alternative is wet etching. The wet etching method has the advantage of lower equipment cost and also much better selectivity to the underlying Si layer. Unfortunately, profile control is more difficult. Generally speaking, in wet etching, two factors must be controlled very well in order to have a good taper profile. The first is a special chemistry to deteriorate the adhesion between the resist mask and the protected material. For example, HNO3 is a well-known agent to achieve this purpose. The second factor is that a good match must be found between the etching chemical and the component material of the multi-layer structure. In other words, the etching rate of the barrier layer and the main conducting layer must be very similar for the same etching chemical. For example, Mo and Al can be etched by the same etching chemical with similar rates. On the contrary, Ti and Al can not be etched with similar rate by a certain chemical. However, a major drawback of the wet etching method for the multi-layer structure is that the match of the rate for different material will drift with the bath life. Moreover, the necessity to add the HNO3 to improve the taper profile will make the situation even more complicated. The above mentioned issues make it not so practical to wet etch the Mo/Al multi-layer structure in spite of the good match of these two material in the same Al etchant.
SUMMARY OF THE INVENTION
Due to above-mentioned issues, it is difficult to etch the multi-layer structured transmission bus in TFT array by wet etching in a very straightforward way. The present invention proposes a simple and practical method to fabricate the multi-layer structured transmission bus in TFT array by using wet etching method. By this method, the taper profile is easier to control in spite of the bath life changes.
The method according to one preferred embodiment of the present invention includes the following steps. Firstly, form a major conductive metallic layer on the substrate or on the previous layers depending on whether gate or source/drain bus is to be formed, then form a barrier layer on the metallic layer with dopant doped into the barrier layer. It is noted that the concentration of the dopant has a gradient distribution, and has a maximum value at the edge of the barrier layer adjacent to the metallic layer. The first edge of the barrier layer adjacent to the metallic layer has a first dopant concentration, and the second edge of the barrier layer farther from the metallic layer has a second dopant concentration. The first dopant concentration is greater than the second dopant concentration. A special feature of this structure is that the wet etching rate of the doped barrier layer can be modulated by the doping concentration. Specifically, the higher the doping concentration, the lower the etching rate is preferred. Because the etching rate of the barrier layer is gradient changed by modulating the doping concentration during film deposition, the taper profile of the barrier layer will be automatically formed without the adjustment of the adhesion to the resist mask. It makes the etching chemistry less complicated and the profile is not sensitive to the bath life. Another feature of this method is that the etching rate of the barrier should be higher than the major metallic conductive layer to avoid the negative slope of the profile.
The method according to another preferred embodiment of the present invention includes the following steps. Firstly, form a major conductive metallic layer on the substrate or on the previous layers depending on whether gate or source/drain bus is to be formed, then form a barrier layer on the metallic layer with dopant doped into the barrier layer. On the doped barrier layer, form one more undoped sacrificial layer with the base material the same as the barrier layer. Because the undoped sacrificial layer has a higher etching rate than the doped layer, the adhesion to the resist mask becomes not so important. This makes the etching chemistry less complicated and thus easier to control.
The transmission bus formed by the said method is electrically coupled to a plurality of transistors of a TFT array. In addition, the plurality of transistors of the TFT array controls the transmittance of the associated LCD cells. The major conductive metallic layer used in the present invention can be made of Al or aluminum alloy such as AlNd. The barrier layer mentioned above can be Mo based material and the dopant can be Nitrogen.
REFERENCES:
patent: 5156986 (1992-10-01), Wei et al.
patent: 5763904 (1999-02-01), Nakajima et al.
patent: 5831281 (1998-11-01), Kurogane et al.
patent: 5872021 (1999-02-01), Matsumoto et al.
patent: 5946547 (1999-08-01), Kim et al.
patent: 6043859 (2000-03-01), Maeda
Chi Mei Optoelectronics Corp.
Deo Duy-Vu
Kunemund Robert
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