Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-09-08
2001-11-13
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S736000, C257S748000, C257S764000, C257S773000, C438S644000, C438S654000
Reexamination Certificate
active
06316834
ABSTRACT:
DESCRIPTION
1. Technical Field
This invention relates generally to the fabrication of integrated circuits, and more particularly to the formation of tungsten plugs used in integrated circuits.
2. Background Art
Over the past several decades, integrated circuits (ICs) have become an integral part of modern electrical devices. As such, processes associated with the development of ICs are constantly being refined to improve both the yield and the quality of ICs. In conventional IC fabrication techniques, after vias are formed in layers of oxide which are deposited over metal layers, tungsten (W) plugs may be formed in the vias to establish connections between a metal layer and an IC device or between different metal layers. Maintaining the planarity of a semiconductor wafer surface during the fabrication of plugs is crucial to provide a suitable surface for any subsequent photo-lithography and other processes.
FIG. 1
a
is a diagrammatic side-view representation of a conventional, partially processed semiconductor wafer
10
. Wafer
10
is mounted on, for example, an electrostatic chuck
11
, which may be provided with backside helium cooling as part of a process for controlling wafer temperature across most of wafer
10
. In the process of fabricating wafer
10
, a layer of oxide
12
is deposited over a semiconductor substrate
14
, and via holes or “vias”
16
, are formed in oxide layer
12
. It should be appreciated that oxide layer
12
may generally refer to any inter-metal dielectric layer, such as an inter-metal oxide layer (IMO). By way of example, an overall IMO layer may include oxide layers and a spin-on glass layer. A “glue layer”
18
, which is typically a titanium nitride (TiN) or titanium tungsten (TiW) layer, can be deposited over oxide layer
12
and within vias
16
to enable a tungsten layer
20
to better “stick,” or adhere, to oxide layer
12
. The prior art process of depositing glue layer
18
results in an essentially uniform glue layer where the thickness of the layer is essentially constant. This essentially constant glue layer thickness is usually such that uniformity in the thickness is maintained to within approximately five percent. That is, the difference between the average glue layer thickness at the edge
24
of wafer
10
and the glue layer thickness at the center (not shown) of wafer
10
is approximately five percent of the glue layer thickness at the center of wafer
10
.
Tungsten layer
20
is eventually etched back to form tungsten plugs in vias
16
. The tungsten etchback process is dependent upon factors which include, but are not limited to, wafer temperature and the composition of plasma used in the etchback process. This etchback is typically done in plasma which contains a fluorinated gas such as sulfur hexaflouride (SF
6
). Once the bulk of the tungsten film
20
is removed, leaving only residual tungsten and tungsten-filled plugs, as will be described with respect to
FIG. 1
b
, glue layer
18
, e.g. a TiN layer, is exposed to the fluorinated plasma.
The etch rate of the residual tungsten has been observed to slow locally once TiN, that is, glue layer
18
, is exposed to the fluorinated plasma. This slowing of the etch rate is generally believed to be a result of the redeposition of titanium fluorides produced from the reaction of the fluorinated plasma with TiN. The titanium fluorides deposit on residual tungsten and block the plasma, thereby locally reducing the etch rate of both tungsten and TiN. As the redeposition mechanism is dependent on temperature, the etch rate of TiN is also dependent upon temperature; higher temperatures prevent redeposition of titanium fluoride and, hence, the etch rates of tungsten and TiN. Thus, if some regions of wafer
10
, as for example edge
24
of wafer
10
, have higher temperatures than other areas, the etch rates of tungsten and TiN will also be higher in those regions. More importantly, if the glue layer etches through in the regions of elevated temperatures, due to the higher local etch rate, any underlying dielectric film, typically a silicon dioxide (SiO
2
) layer, will be exposed to the plasma, SiO
2
etches readily in a fluorinated plasma; hence, oxygen is released into the plasma, thereby accelerating the etch rate of tungsten layer
20
. The acceleration has been observed as being sufficient to locally etch out much or all of tungsten plugs formed during the etching process, as will be described with respect to
FIG. 1
b.
FIG. 1
b
is an enlarged and exaggerated side-view representation of a portion of semiconductor wafer
10
of
FIG. 1
a
after a tungsten etchback process. After the tungsten layer
20
is etched, it is typically desirable for tungsten to remain only within vias
16
so that the surface of the processed wafer is essentially planar in preparation for subsequent processing steps. Within vias
16
, remaining tungsten forms tungsten plugs, as for example tungsten plug
20
a
in via
16
a
. Tungsten plug
20
a
, which is located away from the edge of wafer
10
is representative of a tungsten plug which is formed as desired, as tungsten plug
20
a
is not recessed in via
16
a
. In other words, tungsten plug
20
a
is situated within via
16
a
such that a surface
28
a
of tungsten plug
20
a
is approximately level with the “top” of glue layer
18
and, hence, the “top”
19
of oxide layer
12
.
The effect of chuck
11
is such that the portions of wafer
10
near the edge
22
of chuck
11
are hotter than other portions of wafer
10
. With reference to
FIG. 1
a
, this is due, in part, to the fact that the edge of the wafer
10
overlaps the edge of the chuck
11
and, therefore, is not cooled by the chuck
11
. As described above, the etch rate of glue layer
18
, i.e. TiN layer, increases with temperature. Hence, the portions of glue layer
18
overlapping the edge
22
of electrostatic chuck
11
will etch more quickly than other portions of glue layer
18
. Thus, portions of glue layer
18
near the edge
22
may etch through, thereby exposing oxide layer
12
. As shown, oxide layer
12
is exposed at the edge
24
of wafer
10
.
The enhanced production of fluorine which results from etching through SiO
2
(oxide) layer
12
locally increases the etch rate of tungsten layer
20
. That is, the etch rate of tungsten near the location where oxide is exposed is higher than the etch rate of tungsten in locations away from where oxide is exposed. As such, more tungsten is etched near the edge
24
of wafer
10
where oxide layer
12
is exposed than at portions of wafer
10
away from the edge
24
where oxide layer
12
is exposed. The result of the etching of a larger amount of tungsten near the edge
24
of wafer
10
is the over-etching of tungsten plugs near the edge
24
of wafer
10
, as for example tungsten plug
20
d
. As shown, tungsten plugs which are further from the edge
24
of wafer
10
, as for example tungsten plug
20
c
, are less over-etched or “recessed” than those closer to edge
24
, as for example tungsten plug
20
d
. Similarly, tungsten plug
20
b
, which is still further from edge
24
, is less recessed than tungsten plug
20
c
. Therefore, to completely etch plugs that are not near the edge
24
of wafer
10
(such as plug
20
a
), there is a tendency to over-etch the plugs near the edge
24
(such as plugs
20
b
,
20
c
,
20
d
), resulting in recessed plugs near the edge
24
of wafer
10
.
While the exposure of oxide generally tends to increase the etch rate of tungsten, as mentioned above, the temperature of the semiconductor wafer also has an affect on the etch rate of tungsten. Further, the etch rate of the glue layer, which is typically a TiN layer, is also affected by the temperature of the wafer. A standard measure of the relationship between the etch rate of tungsten and the etch rate of TiN is etch rate selectivity. Etch rate selectivity may be described as the ratio of the tungsten etch rate to the glue layer etch rate.
FIG. 1
c
is a graphical representation of the relationships between tungsten etch rates, TiN etch rates, tung
Gabriel Calvin T.
Lin Xi-Wei
Pramanik Dipankar
Chu Chris C.
Lee Eddie
Oppenheimer Wolff & Donnelly LLP
VLSI Technology Inc.
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