Interconnect and system for making temporary electrical...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S754090, C324S765010

Reexamination Certificate

active

06329829

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and specifically to an interconnect and system for making temporary electrical connections to semiconductor components such as dice, wafers, and chip scale packages.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor components it is sometimes necessary to make temporary electrical connections for testing or other purposes. For example, wafer probe testing requires electrical connections with contact locations (e.g., test pads, bond pads) on a semiconductor wafer. One method for making temporary electrical connections with a semiconductor wafer is with an interconnect known as a “probe card”. Typically probe cards include contacts in the form of metal probe needles. A wafer handler aligns the wafer with the probe card, and places the probe needles in electrical contact with the wafer. Test signals can then be transmitted through the probe needles to test the integrated circuits contained on the wafer.
Singulated semiconductor dice must also be tested in order to certify each die as a known good die (KGD). For testing the dice can be packaged in carriers that include interconnects having contacts for making temporary electrical connections with contact locations on the dice. Chip scale packages also require testing using interconnects adapted to make temporary electrical connections with external contact locations on the packages. For example, some chip scale packages include external contact locations in the form of solder bumps.
In making temporary electrical connections to semiconductor components, interconnects must be adapted to penetrate native oxide layers present on the contact locations. For example, aluminum bond pads on wafers and dice can include oxide layers that must be penetrated to make reliable electrical connections. Contact locations formed of solder, and other alloys, can also include native oxide layers that must be penetrated to contact the underlying metal. Another consideration in making temporary electrical connections to semiconductor components is that the interconnects preferably have compliant characteristics. This helps to prevent excessive contact forces from damaging the contact locations on the component. For example, probe needles have a natural resiliency that allows a probe card to be overdriven in the z-direction with respect to the wafer. The needles are initially placed in “touch” contact with the wafer, and then driven into the contact locations.
If interconnects do not include naturally resilient contacts, compliancy can be achieved with a mounting structure for the contacts. For example, test carriers for bare dice can include resilient biasing members that press against the interconnects or dice, and cushion the contact forces applied by the interconnect contacts. In addition to cushioning contact forces, compliancy can also be used to compensate for dimensional variations among the contact locations on a component, particularly in the z-direction.
The present invention is directed to improved interconnects having naturally resilient contacts. The interconnects can be used to construct wafer level test systems, or die level test systems, and to perform testing methods for semiconductor components.
SUMMARY OF THE INVENTION
In accordance with the present invention, improved interconnects for making temporary electrical connections to semiconductor components are provided. Also provided are methods for fabricating the interconnects, test systems constructed with the interconnects, and test methods employing the interconnects.
In an illustrative embodiment the interconnect comprises: a substrate; electrical conductors formed on the substrate; contact pads formed on the conductors of a non-oxidizing material; and elastomeric contacts formed on the contact pads. The elastomeric contacts can be bumps configured to contact flat contact locations (e.g., bond pads), or alternately recessed members configured to contact bumped contact locations (e.g., solder bumps). In addition, the interconnect can be configured for constructing a wafer level test system for testing semiconductor wafers, or a die level test system for testing singulated dice and chip scale packages.
Suitable materials for forming the substrate include silicon, ceramic, or FR-4 material. The conductors can be formed of a highly conductive metals such as copper, aluminum and tungsten. Suitable materials for forming the contact pads include palladium and gold. The elastomeric contacts can be formed of a conductive elastomeric material, such as silver filled silicone, and anisotropic adhesives. Using conductive elastomers, the elastomeric contacts are naturally resilient to provide compliancy for cushioning contact forces, and for compensating for z-direction dimensional variations in the contact locations. In addition, the resiliency of the elastomeric contacts allows the contacts to be compression loaded during test procedures, while conductive particles therein, penetrate oxide layers covering the contact locations.
A method for fabricating the interconnect includes the steps of: providing a substrate; forming a pattern of conductors on the substrate; forming contact pads on the conductors by plating portions thereof with a non-oxidizing metal; and then forming elastomeric contacts on the contact pads in patterns corresponding to patterns of contact locations on a semiconductor component. The conductors can be formed using a thin film metallization process, or a thick film metallization process. The contact pads can be formed using an electroless deposition process, or using an electrodeposition process. The elastomeric contacts can be formed by stenciling, screen printing or otherwise depositing a viscous conductive elastomeric material in a desired pattern of bumps, followed by partial curing, planarization and then total curing.


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