Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-03-03
2001-05-22
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S155000
Reexamination Certificate
active
06236251
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit provided on a semiconductor chip, and in particular, to a semiconductor integrated circuit operable in synchronization with an external clock signal supplied from outside the semiconductor chip.
2. Description of the Related Art
Conventionally, in a structure in which a semiconductor integrated circuit formed on a semiconductor chip operates in synchronization with an external clock signal supplied from outside the semiconductor chip, a synchronization circuit such as a PLL (Phase-Locked Loop) circuit is used for outputting an internal clock signal in synchronization with the external clock signal. The internal clock signal output by the synchronization circuit is supplied to a plurality of functional blocks formed on the semiconductor chip.
However, it is difficult to completely uniformalize the distances between the synchronization circuit and each of the plurality of functional blocks due to various constrains in laying out the synchronization circuit and the plurality of functional blocks on the semiconductor chip. In the case where the distances between the synchronization circuit and each of the plurality of functional blocks are different from one another, the transfer delays of the internal clocks to the functional blocks vary. Such differences generate a skew of the internal clock signal. The higher the frequency of the external clock signal is, the more serious the skew is.
SUMMARY OF THE INVENTION
A semiconductor Integrated circuit provided on a semiconductor chip according to the present invention includes a first synchronization circuit for receiving an external clock signal supplied from outside the semiconductor chip and outputting a first internal clock signal synchronized with the external clock signal and usable inside the semiconductor chip; a second synchronization circuit for receiving the first internal clock signal and outputting a second internal clock signal synchronized with the first internal clock signal and usable inside the semiconductor chip; and a functional block operable in synchronization with the second internal clock signal.
In one embodiment of the invention, the first synchronization circuit has a first setup time period from when an operation start is requested until the first synchronization circuit starts a synchronization operation, the second synchronization circuit has a second setup time period from when an operation start is requested until the second synchronization circuit starts a synchronization operation, and the second setup time period is shorter than the first setup time period.
In one embodiment of the invention, the first synchronization circuit has a function of adjusting a duty ratio of the first internal clock signal.
In one embodiment of the invention, the second synchronization circuit is a mirror delay-type DLL (Delayed-Locked Loop) circuit including a circuit for advancing a phase of the second Internal clock signal.
In one embodiment of the invention, the semiconductor integrated circuit further includes at least one other second synchronization circuit so as to include a plurality of second synchronization circuits; at least one other functional block so as to include a plurality of functional blocks; and a selection circuit for selecting at least one of the plurality of functional blocks in accordance with a functional block selection signal. The plurality of second synchronization circuits each receive the first internal clock signal and output a second internal clock signal synchronized with the first internal clock is signal and usable inside the semiconductor chip. The plurality of functional blocks are each operable in synchronization with the second internal clock signal which is output from one second synchronization circuit, among the plurality of second synchronization circuits, which corresponds to each of the functional blocks. The plurality of second synchronization circuits are selectively activated in accordance with the functional block selection signal.
In one embodiment of the invention, the plurality of functional blocks include memory cell array blocks each including a row-system circuit for receiving a row address and a column-system circuit for receiving a column address. The row-system circuit is operable in response to the functional block selection signal. The column-system circuit is operable in response to the second internal clock signal.
According to the present invention, a first internal clock signal synchronized with an external clock signal is output by a first synchronization circuit, and a second internal clock signal synchronized with the first internal clock signal is output by a second synchronization circuit. The second internal clock signal is supplied to a functional block. The second synchronization circuit can be located at any position on a semiconductor chip. By locating the second synchronization circuit in the vicinity of the functional block, generation of a skew of the second internal clock signal is avoided regardless of the position of the functional block on the semiconductor chip.
In one embodiment a first synchronization circuit having a first setup time period and a second synchronization circuit having a second setup time period which is shorter than the first setup time period can be used. In the case where a synchronization circuit having a relatively long setup time (e.g., a PLL circuit) and a synchronization circuit having a relatively short setup time (e. g. a mirror delay-type DLL circuit) are combined, the semiconductor integrated circuit operates at a higher speed than in the case where the same type of synchronization circuits having a relatively long setup time period are combined.
In another embodiment, the duty ratio of the first internal clock signal can be adjusted to an appropriate value (typically, 1:1) by the first synchronization circuit. Once the duty ratio of the first internal clock signal is adjusted to be an appropriate value in the semiconductor chip, the probability, that the duty ratio of the second internal clock signal based an the first internal clock signal changes in the semiconductor chip can be ignored in practice. Accordingly, adjustment of the duty ratio of the second internal clock signal can be omitted by adjusting the duty ratio of the first internal clock signal. This allows a synchronization circuit which does not have a function of adjusting the duty ratio of the second internal clock signal to be used as the second synchronization circuit.
In still another embodiment, the phase of the second internal clock signal can be advanced by the mirror delay-type DLL circuit. Thus, the phase of the second internal clock signal at a specified position on the semiconductor chip supplied with the second internal clock signal and the phase of the first internal clock signal input to the second synchronization circuit can be matched to each other.
In still another embodiment, a plurality of second synchronization circuits are selectively activated in accordance with a functional block selection signal. Thus, the number of second synchronization circuits in an active state can be minimized. As a result, an increase in the power consumption of the semiconductor integrated circuit can be prevented.
In still another embodiment, a semiconductor integrated circuit which includes a memory cell array block and prevents an increase in the power consumption can be provided.
Thus, the invention described herein makes possible the advantages of providing (1) a semiconductor integrated circuit for allowing an internal clock signal synchronized with an external clock signal to be supplied to functional blocks arranged on arbitrary positions on the semiconductor chip without generating a skew of the internal clock signal; (2) a semiconductor integrated circuit operable at a high speed in synchronization with an external clock signal; and (3) a semiconductor integrated circuit operable at a low power consumption in synchroniz
Matsushita Electric - Industrial Co., Ltd.
Nguyen Hai L.
Renner Otto Boisselle & Sklar
Wells Kenneth B.
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