Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1998-08-07
2001-11-27
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185260, C365S189011, C257S315000
Reexamination Certificate
active
06324101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a storage device and, more particularly, to a storage device using a semiconductor.
2. Related Background Art
In recent years, along with the development of information/video industries, media and devices for storing information have been extensively developed. Of these media and devices, storage devices such as DRAMs, SRAMs, and the like have large storage capacities even though they have compact, lightweight, and low-power structures, and allow high-accuracy read/write operations at high speed. For these reasons, these devices are used in equipment in various fields.
Also, recently, a storage device, a so-called flash memory, which is programmable and can hold information, has received a lot of attention. This storage device is superior to the DRAM in terms of the degree of integration.
On the other hand, an OT-PROM (one time PROM) in which information can be written only once has been proposed in Japanese Laid-Open Patent Application No. 62-188260 (inventor: Levi Gersburg (phonetic)) and Japanese Laid-Open Patent Application No. 62-49651 (inventors: Brian E. Cook, Douglas P. Berlet (phonetic)). In the arrangement of the OT-PROM, a wiring metal is connected in series with a main electrode (the source or drain for a MOSFET; the emitter for a bipolar transistor) of a transistor via an a-Si layer. By changing the a-Si layer from a high-resistance state to a low-resistance state, a storage operation is achieved.
However, a storage device such as a DRAM using a semiconductor has the following problems.
1. Semiconductor storage devices like DRAMs and SRAMs suffer from a high rate of chip cost increase with any increase in storage capacity, and also suffer from a higher bit cost than those of floppy disks, magnetic tapes, and CD-ROMs. For these reasons, such a storage device cannot be used practically as a storage medium.
2. At present, the storage capacity is at the 256-Mbit level even at the research level, which is insufficient information volume for images.
3. When information is stored in a DRAM or SRAM, the DRAM or SRAM must be kept supplied with a power supply voltage, and it is therefore difficult to use such circuits in portable equipment. Under these circumstances, a battery built-in device is used in such equipment.
On the other hand, the flash memory, which is superior to the DRAM and the like in terms of degree of integration, also has the following problems.
1. Since a charge is written in or erased from a floating gate by injection of an FN tunnel current, hot electrons, or the like, the reliability of the insulating layer which is subjected to a charge input/output operation is degraded as the number of times of use increases.
2. The FN tunnel current density, J, is expressed by:
J=&agr;E
2
exp(−&bgr;/
E
) (1)
where E is the electric field to be applied to the insulating layer, and a and &bgr; are constants. From equation (1), a large current flows when the electric field strength is large. However, as the floating gate potential changes, the current decreases exponentially. Therefore, the write or erase time per bit is as long as about 100 &mgr;s to 10 ms, resulting in poor operability of the storage device.
3. The FN tunnel current strongly depends on the film quality and thickness of the insulating film, and the proper write or erase time undesirably varies among samples and bits. For this reason, in practice, after chips are manufactured, the chips are classified into groups in an inspection process, and are operated at timings suitable for these groups. Thus, the load on the inspection process is heavy, resulting in high cost.
4. As the storage capacity increases, the floating gate area decreases. For this reason, the floating gate capacity decreases proportionally, and the floating gate potential changes considerably due even to a small leakage current. Therefore, in order to assure a desired capacity, an affordable reduction in floating gate area is limited, and this limitation interferes with the need to increase capacity.
Furthermore, the OT-PROM in which information can be written only once is excellent in that its state after information is written does not change permanently and is stable. However, the OT-PROM requires an a-Si layer and a contact area between the a-Si layer and a wiring layer for each bit. In a semiconductor process, formation of contact holes is difficult to achieve as compared to formation of line patterns. Even if a 0.8-&mgr;m rule process is used, the contact size is on the 1-&mgr;m
2
order which is about 20% larger than 0.8 &mgr;m. Since the wiring width must be larger than each contact hole, the area per bit cannot be reduced. For these reasons, it is difficult to realize a large storage capacity in the proposed memories. Also, since a large current flows through the a-Si layer in a write operation, the consumption of power is high, and it is difficult to apply such a memory to portable equipment.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a storage device, which can solve the above-mentioned technical problems, and can realize a large capacity, low cost, write enable, high read/write speed, high reliability, and low consumption power.
The above-mentioned object can be realized by the following device.
In a first storage device of the present invention, which comprises, on a substrate, a first semiconductor region of one conductivity type, second and third semiconductor regions of a conductivity type opposite to the one conductivity type, which are contiguous to the first semiconductor region, a first electrode which is formed on a region for isolating the second and third semiconductor regions via an insulating layer, and a second electrode formed on the first electrode but spaced therefrom by an insulating layer, a resistance between the first and second electrodes is changed from a high-resistance state to a low-resistance state.
In a further aspect of the present invention, the change in resistance is attained by a voltage to be applied to the second electrode.
In another aspect of the invention, a plurality of such storage devices are arranged, and the i-th second or third semiconductor regions and (i+1)-th third or second semiconductor regions of the plurality of storage devices are electrically connected to each other.
In still another aspect of the present invention, a plurality of such storage devices are arranged, the second semiconductor regions of the plurality of storage devices are connected to each other, and the third semiconductor regions thereof are connected to each other.
In still another aspect of the present invention, the substrate comprises a substrate which has an Si layer on an insulating layer.
In yet another aspect of the present invention, several such storage devices are arranged in a matrix, a line for commonly connecting the second electrodes in one direction of arrays is arranged, the first semiconductor regions of the storage devices arranged in a direction perpendicular to the line are commonly connected, and the first semiconductor regions in the respective arrays are electrically isolated from each other.
In still another aspect of the present invention, an opposing area between the first electrode and a semiconductor region having the first, second, and third semiconductor regions is larger than an opposing area of the second electrode and the first electrode.
In yet another aspect of the present invention, the first electrode has at least two opposing portions which sandwich the first semiconductor region therebetween.
In yet another aspect of the present invention, the first electrode consists of a material containing poly-Si.
In still another aspect of the present invention, an insulating layer between a semiconductor region including the first, second, and third semiconductor regions, and the first electrode comprises a film consisting of Si, N, and O.
In yet still another aspect of the present invention, the storage device comprises a stor
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Ho Hoai V.
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