Self-timed semiconductor integrated circuit device

Details Self-timed semiconductor integrated circuit device Self-timed semiconductor integrated circuit device

1999-02-08

2001-05-29

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S293000, C327S296000

Reexamination Certificate

active

06239628

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated-circuit device, which, for example, may include a data processing device such as a microprocessor or a data storage device such as memory, wherein, while data is being transmitted thereto and therefrom, the presence/absence of a data flow is self-monitored and self-timed is carried out in the course of the data transmission.
A semiconductor integrated-circuit device embracing the first conventional technology is shown in FIG.
12
. The semiconductor integrated-circuit device shown in the figure controls a plurality of functional logical blocks using clock signals.
A data path has a configuration comprising separated bits. For example, functional logical blocks F
11
, F
12
and F
13
associated with the first bit are each sandwiched by latches placed before and after it. Each functional logical block operates synchronously with a clock signal. The functional logical blocks and latches associated with the second to nth bits are arranged in the same way as those for the first bit. The principle of operation is described by referring to a timing-chart shown in FIG.
18
. Let us begin with the first bit. The functional logical block F
11
inputs data from a latch
150
on the rising edge of a clock (a). The processing of the data must be finished and a result to be supplied to a latch
151
must be set up within a time shorter than the period T of the clock. Much like the functional logical block F
11
, the functional logical block F
12
inputs data from a latch
151
on the rising edge of the clock. Similarly, the processing of the data must be finished and a result to be supplied to a latch
152
must be set up within a time shorter than the period T of the clock. As shown in the figure, the functional logical blocks for the 2nd to nth bits operate with the same timing. By the way, the clock signal is actually distributed through metal wires laid out two-dimensionally. Accordingly, the timing varies from location to location. Let a skew tsk be the width of the timing discrepancy and t
F11
be a period of time between the rising edge of the clock for the latch
150
and a point of time at which the data supplied to the latch
151
is set. In this case, the following inequality must be satisfied:
t
F11
<T−t
sk
  (1)
Similarly, it is necessary for a functional logical block of any nth bit at any mth stage, where n and m are integers, to satisfy the same equality as the above as follows:
t
Fnn
<T−t
sk
Accordingly, the clock period T is determined by the longest data processing time among all functional logical blocks. As a result, if the data processing times of all the functional logical blocks can be made about equal to each other, the clock period T can be made shortest.
A self-timed computing element in place of the computing element synchronized by a clock signal as described above is disclosed, for example, in a Stanford technical report entitled “Self-Timed Rings and their Application to Divison” CSL-TR-91-482, written by T. Williams in May 1991. Refer to FIG.
10
.
A precharge functional block F
2
starts processing as soon as the block F
2
receives information on the completion of the resetting of a block F
3
at the following stage. The functional block F
3
detects the completion of its resetting by itself, transmitting a detection signal to the block F
2
at the preceding stage. By using such a self-synchronizing system, the delay time caused by a clock skew can be eliminated.
In the first conventional system example, each functional logical block operates synchronously with a clock signal. In such a clock-synchronized system, the period T of the clock signal is at least equal to the sum of the longest data processing time among all the functional logical blocks and the clock skew in accordance with Inequality (1). Accordingly, the operation frequency, the inverse number of the clock period T, is decreased by an amount determined by the clock skew.
In general, the performance of a system is proportional to the operation frequency. Accordingly, a problem that the performance is degraded by the clock skew exists. It is obvious from Inequality (1) that the clock period T is inevitably increased by the clock skew t
sk
.
On top of that, the system must be designed so that the times required by all the functional logical blocks are about equal to each other. As a result, the system design becomes inevitably complicated.
In the case of the second conventional system example, on the other hand, a precharge functional block in only one data path is described to be either in a precharge or discharge state depending upon whether or not data is passing through the block. As for a plurality of data paths, there is no description whatsoever. In other words, the synchronization of the data paths associated with a plurality of bits for example is not described at all.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a system with a configuration wherein a plurality of data paths operate synchronously and the data paths are not affected by the clock skew.
The present invention provides a self-timed semiconductor integrated-circuit device characterized in that:
said self-timed semiconductor integrated-circuit device comprises at least two logic-circuit blocks for performing logical operations;
said logic-circuit blocks are connected to each
other by data paths;
said data paths each have data-flow detecting units at data input units and data output units of said logic-circuit blocks connected thereby;
as data output by the nth of said logic-circuit blocks, where n is an integer equal to or greater than unity, through said data path connected thereto, said nth data-flow detecting unit of said data path generates an nth data-flow detecting signal indicating a flow of said data, supplying said nth data-flow detecting signal to the (n−1) th or (n+1)th of said logic-circuit blocks; and
said nth data-flow detecting signal is used for controlling said (n−1)th or (n+1)th logic-circuit block.
With the configuration provided by the present invention as described above, the operation of another functional logical block connected to a data path can be controlled depending upon whether or not the flow of data exists; allowing a self-synchronizing semiconductor integrated-circuit device for executing data processing without relying on a clock signal to be realized.


REFERENCES:
patent: 4424581 (1984-01-01), Kawai
patent: 4661922 (1987-04-01), Thierbach
patent: 4697279 (1987-09-01), Baratti et al.
patent: 4839604 (1989-06-01), Tanahashi
patent: 4951301 (1990-08-01), Zulian
patent: 5150364 (1992-09-01), Negus
patent: 5416807 (1995-05-01), Brady et al.
patent: 5481554 (1996-01-01), Kondo

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